Layout Engineer (Engineer/Lead/Senior)

PragmatIC Semiconductor; Cambridge; On-site; GBP 125,000 - 150,000; Full time

Job summary

A tech semiconductor company in Cambridge is looking for a Layout Engineer to join their IC Engineering team. This role involves collaborating across multiple teams to produce high-quality layouts that will support the company's product roadmap. Candidates should have experience in transistor level designs and a solid understanding of layout challenges. The company offers a competitive benefits package, including visa sponsorship. Embrace a supportive environment that values equity and inclusion.

Benefits

Visa sponsorship/relocation support

Competitive benefits package

Qualifications

• Demonstrable experience of transistor level designs from scratch.
• Excellent understanding of layout challenges such as parasitics, matching, and shielding.
• Proficiency in Cadence development tools.

Responsibilities

• Work in partnership with analogue designers for high quality layouts.
• Complete Analog-on-Top chip level layout floor planning.
• Perform block and chip level verifications using industry standard tools.

Skills

Transistor level designs

Layout challenges awareness

Library development

Design tools proficiency

DRC/LVS verification

Communication skills

Education

Degree / Postgraduate degree

Tools

Cadence Virtuoso

Job description

Overview

We have an excitingopportunity for a Layout Engineerto join the excellent IC Engineering team at Pragmatic Semiconductor. Based in Cambridge and reporting to the Senior Manager - IC Layout, the successful candidate will collaborate with multiple teams to produce high quality layouts and significantly support the progress ofour Product roadmap.

You will be part of a supportive Layout team and wider IC Engineering function, working on all aspects of Layout, which includes supporting bothpresent and future generation technologies by providing top level chip designs.

We are looking for candidates ideally with broad experience of the full Layout process flow, and a solid understanding of parasitics(using methodologies such as routing, matching and shielding) and verification (using LVS, DRC etc). We are open-minded on the level of the position, so will be happy to consider candidates from a variety of experience ranges.

We are offering a highly attractivebenefits package for this position, including Visa sponsorship/relocation support to the UK (Cambridge).

Key tasks

• Work in partnership with analogue designers to deliver high quality layouts to support Pragmatic’s product roadmap
  
• Complete Analog-on-Top Chip level layout floor planning, integration and tape-out activities
  
• Performing details transistor level layout designs for Custom Analog Block-IP, such as PLL’s and ADC’s etc
  
• Developing Logic libraries/IO and memory library from scratch based on latest Pragmatic technology and process updates
  
• Perform block and chip level verifications such as LVS / DRC / Extraction using industry standard verification tools.
  
• Active participation in the Design Review process, documentations and ownership the designs
  
• Develop a strong understand of the PDK and design requirements in order to create high quality layouts
  
• Develop DTCO test chips on new technologies and process
  
• Work with our process teams to develop and guide DFM rules
  
• Support R&D team on the next-generation technology

Qualifications and training

The successful candidate will ideally be educated to degree / Postgraduate degree level, or will possess equivalent experience.

Skills and experience

ESSENTIAL

• Demonstrable experience of Transistor level designs from scratch
• Excellent understanding of layout challenges such as parasitics, matching, shielding etc.
• Strong knowledge of library development (IO/Logic/Memory) from scratch.
• Good understanding of custom layouts like PLL’s and ADC’s.
• Well versed in using industry standard design tools (such as Cadence Virtuoso) and verification tools
• Good understanding of DRC, LVS verification and industrial standard tools
• Proficiency in Cadence development tools and interpretation of verification tools
• Clear understanding of layout considerations, layout parasitic and their impact
• Excellent communication skills and ability to interact effectively with cross-functional teams such asDesign, R&D, PDK and Modelling.

DESIRABLE

• Solid understanding of a programming language like SKILL, Tcl etc would be beneficial

Candidates who do not meet every requirement but feel their skills are a good fit for the role the role are encouraged to apply.

Pragmatic is committed to equity, equality, diversity, and inclusion; we strive to welcome everyone and create inclusive teams. We celebrate difference and encourage everyone to be themselves at work. Please let us know if you would like any adjustments to our application and interview process.