ASIC Design and Implementation Engineer – Compute DSP/AI Processors

Qualcomm; Markham; On-site; CAD 143,000 - 213,000; Full time

Job summary

A leading technology company is seeking an ASIC Design and Implementation Engineer to join their Compute DSP/AI Processor Design Team in Markham, Canada. This role involves developing hardware for AI/ML processing systems in Snapdragon processors. Candidates should hold a relevant engineering degree and have over 3 years of experience with ASIC design. The pay range is $104,900 - $154,900 annually, along with competitive benefits and bonuses.

Benefits

Competitive annual discretionary bonus

RSU grants

Qualifications

• 3+ years ASIC design and netlist implementation experience.
• Experience with various scripting languages like TCL, Python, and Perl.
• Ability to work on-site in Markham, Canada.

Responsibilities

• Develop module and floor planning specifications for digital compute processing cores.
• Investigate performance and design tradeoffs for hard macros.
• Implement and debug timing constraints, RTL, DFT, and clock functions.
• Perform netlist synthesis and Static Timing Analysis.
• Develop methodology for design/synthesis using scripts.

Skills

High-speed logic design

Power optimization

Analytical skills

Collaboration

Debugging skills

Communication skills

Education

Bachelor's degree in Engineering, Science, or related field

Tools

Synopsys FC

Cadence Genus

Primetime

UPF

TCL

Python

Job description

Company: Qualcomm Canada ULC

Job Area: Engineering Group > ASICS Engineering

General Summary

Qualcomm enables a world where everyone and everything can be intelligently connected. As the world's leading wireless tech innovator, we push the boundaries of what's possible to enable next‑gen experiences and drive digital transformation for a smarter, connected future.

We are searching for an ASIC Design and Implementation Engineer to be part of the Compute DSP/AI Processor Design Team responsible for developing hardware to support AI/ML and video processing systems in Qualcomm Snapdragon processors.

This is a New Position.

Principal Duties and Responsibilities

• Develop module, hard‑macro, and floor planning specifications for digital compute processing cores, bus interfaces, and other system‑on‑chip functions
• Investigate, analyze, and present performance, area, power, and system cost tradeoffs for hard macros using constraint, timing, and floorplan driven optimizations
• Contribute to and/or drive floor planning and implementation meetings within a multi‑disciplinary team
• Implement and debug timing constraints, RTL, Power Intent Specification, Design for Test (DFT), and clock functions
• Perform netlist synthesis, Formal Verification, and Static Timing Analysis of hard macros
• Implement ECOs using automated design flows
• Complete design checks and analysis such as lint, CDC, power intent, and static timing reports
• Develop methodology and automation for design/synthesis using TCL/make/python scripts

Minimum Qualifications

• Bachelor's degree in Engineering, Science, or related field
• 3+ years ASIC design and netlist implementation experience
• Legally permitted to work on‑site in Markham, Canada

Preferred Qualifications

• Proven experience implementing high‑speed logic designs with RAM and several clock domains
• Strong verbal and written communication skills to concisely evaluate and deliver specifications, plans, and design analyses
• Detail oriented with strong analytical, critical thinking, and debugging skills
• Collaborative and able to adapt to challenging team objectives in a multi‑national organization
• Understanding of ASIC/VLSI design concepts
  • Bus interfaces (AHB/AXI)
  • Clock crossing
  • RAM and FIFO integration
  • ASIC clock network analysis
  • Static timing analysis debug strategy
  • Timing constraints development and debug
  • Power optimization
• Proven design and implementation skills using several of the following languages and tools
  • Synthesis: Synopsys FC (or DCG/NXT), Cadence Genus
  • Static Timing: Primetime
  • Power Intent and Analysis: UPF, CLP, PTPX, PowerPro
  • Formal Verification: Conformal, Formality
  • Design/DV: RTL, VCS, Verdi, Questa, Xcelium, Spyglass
  • Scripting Languages: TCL, Python, Perl, UNIX shell

Pay range and Other Compensation & Benefits

$104,900.00 - $154,900.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and the opportunity for annual RSU grants.

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, contact disability‑[e-mail].