Senior ASIC Timing & Physical Design Engineer

Synopsys, Inc.; Elsene; On-site; EUR 70,000 - 120,000; Full time

Benefits offered by this job

Health benefits

Wellness benefits

Financial benefits

Job summary

Synopsys, Inc. in Brussels seeks an experienced timing closure engineer to own static timing analysis for high-performance memory IP and SoC designs. You will work across process corners, implement automation, and collaborate with physical design, RTL, and verification teams to hit aggressive targets.

You bring 5–9 years of STA experience, strong Python and Tcl scripting, and deep knowledge of PrimeTime, PTECO, and DMSA. Join a global team shaping next‑gen silicon in a fast-paced environment.

Qualifications

• 5–9 years of hands-on static timing analysis experience on chip-level or IP-level timing closure.
• Strong knowledge of PrimeTime, PTECO and distributed multi-scenario analysis tools.
• Proven track record closing timing on high-performance designs such as memory IP (DDR/LPDDR/HBM).

Responsibilities

• Close timing on high performance memory IP including DDR, LPDDR, and HBM across corners and modes.
• Own static timing analysis from constraint development through final signoff.
• Debug complex timing violations, including asynchronous crossings and multi-corner issues.
• Implement ECOs to fix functional bugs without destabilizing closed paths.
• Build and maintain automation scripts in Python, Tcl, Perl, and shell to streamline STA workflows.
• Collaborate with physical design, RTL, and verification teams across global sites.

Skills

Python scripting

Shell scripting

Timing analysis

STA tools

Multi-corner closure

Education

Bachelor's or Master's in Electronics Engineering / Electrical Engineering / Computer Science

Tools

PrimeTime

PTECO

DMSA

Job description

Synopsys, Inc. in Brussels seeks an experienced timing closure engineer to own static timing analysis for high-performance memory IP and SoC designs. You will work across process corners, implement automation, and collaborate with physical design, RTL, and verification teams to hit aggressive targets.

You bring 5–9 years of STA experience, strong Python and Tcl scripting, and deep knowledge of PrimeTime, PTECO, and DMSA. Join a global team shaping next‑gen silicon in a fast-paced environment.