Senior Physical Design Engineer

Nalys; Vlaams-Brabant; On-site; EUR 120,000 - 180,000; Full time

Job summary

Nalys is seeking a Principal Physical Design Engineer to lead advanced SoC/IP physical design from RTL to GDSII, including floorplanning, power integrity, P&R, CTS, and STA. You will drive low-power strategies and standardize flows.

You will mentor engineers, optimize design methodologies, and evaluate next‑gen EDA tools to boost efficiency and quality in a fast-paced semiconductor environment. Jointly with architecture and verification teams, you will solve complex technical challenges.

Qualifications

• Minimum 15 years in ASIC physical design with tape-out records.
• Expertise in floorplanning, place & route, clocking and STA.
• Strong problem-solving and leadership in a fast-paced team environment.

Responsibilities

• Lead physical design from RTL to GDSII.
• Own floorplanning, power distribution, P&R, and clock tree synthesis/STA.
• Collaborate with architecture/verification teams to ensure robust implementations.
• Mentor engineers and drive design methodologies and automation.

Skills

ASIC physical design

Tape-out experience

EDA tool proficiency

Scripting (Tcl/Perl/Python)

P&R and STA knowledge

DFM knowledge

Education

Bachelor's or Master’s in EE/Electrical Engineering

Tools

Cadence Innovus/Tempus

Synopsys Fusion Compiler/PrimeTime

Ansys RedHawk/PathFinder

Job description

Nalys is a highly dynamic engineering and technology consulting company dedicated to high-tech projects, providing specialized expertise to top industry players. We are currently recruiting on behalf of a major client in the semiconductor industry, focusing on the development of cutting-edge SoC (System on Chip) and IP blocks.

Job Description

As a Principal Physical Design Engineer consulting for Nalys, you will act as a core technical leader responsible for steering and executing complex physical design activities for advanced SoC and IP blocks. You will take full ownership of the physical implementation from RTL to GDSII, handling critical tasks such as floor planning, power distribution, place and route, clock tree synthesis, and static timing analysis (STA). Your expertise will be crucial in meeting stringent power, performance, and area constraints for next-generation semiconductor products.

In this role, you will proactively optimise workflows, design methodologies, and automation scripts to boost overall engineering efficiency, reduce turnaround times, and elevate design quality. You will collaborate closely with cross-functional architecture and verification teams to troubleshoot complex technical roadblocks and guarantee robust, flawless implementations. Furthermore, you will define comprehensive low-power strategies—including clock gating, power gating, and multi-voltage designs—while actively evaluating next-generation EDA tools to enhance the team's capabilities. A key aspect of your role involves mentoring fellow engineers, sharing your deep technical knowledge, and fostering continuous growth within the physical design department.

Profile / Requirements

We are seeking a highly accomplished engineering professional holding a Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a closely related technical field. You must bring a minimum of 15 years of experience in ASIC physical design, highlighted by a proven track record of successful tape-outs on advanced process nodes.

Deep, hands-on proficiency with industry-standard EDA tools (such as Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, or Ansys RedHawk/PathFinder) is mandatory. You must possess advanced programming skills in scripting languages like Tcl, Perl, or Python to drive complex flow automation. A comprehensive understanding of semiconductor physics, Design for Manufacturability (DFM) principles, and static timing analysis constraints is essential. You are recognised for your outstanding analytical problem-solving capabilities, your ability to lead ambitious technical initiatives, and your dedication to guiding and supporting team members in a fast-paced, collaborative environment.