Senior ASIC Physical Implementation Engineer

Imec; Vlaams-Brabant; Remote; EUR 90,000 - 140,000; Full time

Job summary

Imec in Leuven is seeking a Physical ASIC Design Implementation Engineer to drive the full Cadence Innovus place-and-route flow for advanced nodes (12–5nm). You will work directly with customers and the Back-End team to deliver tape-outs, including floorplanning, power grid design, and timing closure.

Candidates hold a Master in Electronics with at least 8 years in physical implementation, experience with UPF, STA, clock-tree synthesis, DRC/ERC/LVS, and strong English communication in

Qualifications

• Master's degree in Electronics is required.
• 8+ years of experience in physical implementation in advanced nodes (12–5nm) and hierarchical designs.
• Experience with power reduction techniques such as gated clocks, voltage domains, memory retention and power-down domains.
• Experience debugging any tool/flow/design issue.
• Excellent communication skills in English and ability to work in an international team.
• Able to interact with customers.

Responsibilities

• Set up the Cadence Innovus Place & Route flow for the specific libraries and foundry node used.
• Set up low power design (UPF).
• Floorplanning and power grid design.
• Detailed Timing Driven Placement.
• STA and timing optimization for setup.
• Clock Tree Synthesis.
• Scan chain re-stitching.
• Detailed Timing Driven Route (incl. SI).
• In-place optimization (IPO) to achieve timing in all corners.
• Resolve setup and hold violations.
• Sign-off extraction (SPEF/QUANTUS).
• Sign-off timing (TEMPUS).
• Sign-off Power analysis (VOLTUS).
• Physical verification (DRC, ERC, LVS, ANT).
• Logic equivalence check.
• Lead hierarchical design partitioning and coordinate sub-block timing budgets.

Skills

Power reduction techniques

Debugging

Communication skills

Customer interaction

English proficiency

Education

Master Degree in Electronics

Tools

Cadence Innovus

TEMPUS

VOLTUS

DRC/ERC/LVS/ANT

Job description

Imec in Leuven is seeking a Physical ASIC Design Implementation Engineer to drive the full Cadence Innovus place-and-route flow for advanced nodes (12–5nm). You will work directly with customers and the Back-End team to deliver tape-outs, including floorplanning, power grid design, and timing closure.

Candidates hold a Master in Electronics with at least 8 years in physical implementation, experience with UPF, STA, clock-tree synthesis, DRC/ERC/LVS, and strong English communication in