RTL Design Engineer for High-Performance ASICs

Vivid Resourcing Ltd; Vlaams-Brabant; On-site; EUR 70,000 - 105,000; Full time

Job summary

Vivid Resourcing Ltd is seeking a Digital IC Design Engineer in Belgium to contribute to RTL development and advanced ASIC projects, from concept through verification. You will translate architectural specifications into high-quality RTL designs and collaborate across architecture, verification, physical design and validation teams to deliver robust silicon.

The role emphasizes Verilog/SystemVerilog proficiency, RTL simulation, debugging, and design reviews, with responsibility for performance,

Qualifications

• Master's degree in Electronics/Electrical Eng, CS or related.
• Experience in Digital IC Design with RTL emphasis.
• Strong proficiency in Verilog/SystemVerilog.
• Solid understanding of digital design, logic, and microarchitecture.
• Experience with RTL simulation, debugging and verification.
• Familiarity with ASIC design flows (synthesis and physical).
• Knowledge of timing constraints, clock domains and low-power design.
• Experience with industry-standard EDA tools.
• Strong analytical and problem-solving skills in a multidisciplinary team.

Responsibilities

• Develop, implement and maintain RTL designs using Verilog and SystemVerilog.
• Translate specifications into synthesizable RTL.
• Contribute to microarchitecture definition and design docs.
• Optimize RTL for performance, power and area.
• Collaborate with verification engineers for functional verification.
• Work with synthesis and physical design teams for implementation.
• Perform RTL simulation, debugging and design reviews.
• Support full ASIC development lifecycle from spec to silicon validation.
• Identify and resolve design issues ensuring quality and reliability.

Skills

RTL development

Verilog/SystemVerilog

Digital design principles

Timing/clock domains

Problem-solving

Education

Master's degree in Electronics Eng / Electrical Eng / CS

Tools

Industry-standard EDA tools

Job description

Vivid Resourcing Ltd is seeking a Digital IC Design Engineer in Belgium to contribute to RTL development and advanced ASIC projects, from concept through verification. You will translate architectural specifications into high-quality RTL designs and collaborate across architecture, verification, physical design and validation teams to deliver robust silicon.

The role emphasizes Verilog/SystemVerilog proficiency, RTL simulation, debugging, and design reviews, with responsibility for performance,