Principal Physical Design Engineer

IC Resources; Vlaams-Brabant; On-site; EUR 90,000 - 130,000; Full time

Job summary

IC Resources is recruiting a Principal Physical Design Engineer for a Leuven, Belgium-based client. The role covers the full RTL-to-GDS flow with hands-on implementation, optimization, and timing closure for complex ASIC/SoC designs.

You will provide technical guidance and mentoring within the Physical Design team, work with architecture, digital design and verification, and drive improvements to EDA flows and backend methodologies. The position is on-site in Leuven.

Qualifications

• Experience across full RTL-to-GDS flow with tape-out track record.
• Proficiency with Cadence or Synopsys tool suites.
• Strong understanding of timing closure and physical implementation.
• Ability to mentor peers in a Physical Design team.

Responsibilities

• Lead complete physical design flow from RTL to GDS.
• Drive timing closure, power integrity and area targets.
• Develop and improve physical design methodologies and automation.
• Collaborate with architecture, digital design and verification teams.
• Provide technical guidance to other PD engineers.

Skills

RTL-to-GDS flow

Synthesis

Floorplanning

Place & Route

CTS

STA

Physical Verification

Low-Power Design

Technical Leadership

Education

Bachelor's or Master's in Electrical/Electronics

Tools

Cadence

Synopsys

Job description

Principal Physical Design Engineer - Leuven

This client is looking for a Principal Physical Design Engineer to join their semiconductor R&D team in Leuven, working on the physical implementation of complex ASIC and SoC designs.

This is a hands‑on Principal Physical Design Engineer position covering the full RTL-to-GDS flow, with responsibility for implementation, optimisation, timing closure and backend methodology development. The role also offers the opportunity to provide technical guidance and mentoring to other engineers without moving into a formal people management position.

Key responsibilities

• Lead and execute the complete physical design flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and physical verification
• Drive optimisation of designs against challenging performance, power and area targets
• Analyse and resolve complex timing and implementation challenges across advanced digital designs
• Develop and improve physical design methodologies, flows and automation to improve efficiency and design quality
• Work closely with architecture, digital design and verification teams to identify and resolve implementation issues
• Contribute to design and architecture reviews from a physical implementation perspective
• Provide technical guidance and mentoring to other Physical Design Engineers
• Support the adoption and optimisation of EDA tools and backend methodologies

Position Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Microelectronics or a related field
• Strong experience across the complete RTL-to-GDS flow, with a proven track record of successful tape-outs
• Strong experience with industry-standard EDA tools, with expertise in either Cadence or Synopsys
• Strong understanding of STA, timing closure and physical implementation methodologies
• Experience with low‑power design techniques and optimisation
• Experience providing technical leadership or mentoring within a Physical Design environment

Email - [e-mail]

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/