ASIC Physical Design, Staff Engineer

Synopsys; Elsene; On-site; EUR 70,000 - 120,000; Full time

Benefits offered by this job

Health benefits

Wellness benefits

Financial benefits

Job summary

Synopsys, Inc. in Brussels seeks an experienced timing closure engineer to own static timing analysis for high-performance memory IP and SoC designs. You will work across process corners, implement automation, and collaborate with physical design, RTL, and verification teams to hit aggressive targets.

You bring 5–9 years of STA experience, strong Python and Tcl scripting, and deep knowledge of PrimeTime, PTECO, and DMSA. Join a global team shaping next‑gen silicon in a fast-paced environment.

Qualifications

• 5–9 years of hands-on static timing analysis experience on chip-level or IP-level timing closure.
• Strong knowledge of PrimeTime, PTECO and distributed multi-scenario analysis tools.
• Proven track record closing timing on high-performance designs such as memory IP (DDR/LPDDR/HBM).

Responsibilities

• Close timing on high performance memory IP including DDR, LPDDR, and HBM across corners and modes.
• Own static timing analysis from constraint development through final signoff.
• Debug complex timing violations, including asynchronous crossings and multi-corner issues.
• Implement ECOs to fix functional bugs without destabilizing closed paths.
• Build and maintain automation scripts in Python, Tcl, Perl, and shell to streamline STA workflows.
• Collaborate with physical design, RTL, and verification teams across global sites.

Skills

Python scripting

Shell scripting

Timing analysis

STA tools

Multi-corner closure

Education

Bachelor's or Master's in Electronics Engineering / Electrical Engineering / Computer Science

Tools

PrimeTime

PTECO

DMSA

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years staring at timing reports that most people would find incomprehensible, and somewhere along the way you developed an instinct for what will break before it actually does. High performance memory IP like DDR, LPDDR, and HBM does not forgive sloppy timing closure, and you know that the difference between a design that ships and one that gets re-spun is usually a constraint you caught at 2am or a corner case you refused to ignore.

You are the engineer who gets pulled into the room when timing looks impossible. Not because you have magic, but because you know how to read between the setup and hold violations, prioritize what actually matters, and script your way out of manual tedium. You have debugged asynchronous crossings enough times to know when a waiver is justified and when it is just wishful thinking.

Automation is not a nice-to-have for you, it is how you stay sane. You write Python and Tcl scripts that do the repetitive work so you can focus on the hard decisions. At Synopsys, you will work on memory and SoC IP that powers some of the most performance-critical silicon in the industry, and the timing closure work you do will directly determine whether those designs meet their targets.

What You'll Be Doing

• Close timing on high performance memory IP including DDR, LPDDR, HBM, and SoC designs across multiple process corners and operating modes
• Own static timing analysis from constraint development through final signoff using PrimeTime, PTECO, and DMSA
• Debug and resolve complex timing violations including asynchronous domain crossings, multi-corner convergence issues, and setup/hold trade-offs
• Implement engineering change orders to fix functional bugs and timing failures without destabilizing already-closed paths
• Build and maintain automation scripts in Python, Perl, Tcl, and shell to streamline STA workflows, report generation, and ECO implementation
• Collaborate with physical design, RTL, and verification teams across global sites to ensure timing, power, and area requirements are met
• Drive quality and efficiency improvements in the RTL2GDS flow by identifying bottlenecks and proposing tooling or methodology changes

The Impact You Will Have

• Enable Synopsys memory and SoC IP to meet aggressive performance targets that customers depend on for next-generation products
• Reduce design re-spins by catching timing issues early and implementing robust constraint strategies that hold through tapeout
• Accelerate timing closure cycles across multiple projects by building reusable automation that eliminates manual, error-prone tasks
• Improve cross-functional alignment by translating timing analysis into actionable guidance for physical design and RTL teams
• Contribute to the quality and competitiveness of Synopsys IP portfolio through rigorous timing signoff and methodology discipline
• Mentor engineers on timing closure best practices, constraint development, and effective use of STA tools
• Shape the evolution of internal STA flows and tooling based on real challenges you encounter in high performance designs

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Electrical Engineering, Computer Science, or related field
• 5 to 9 years of hands‑on experience in static timing analysis, with a focus on chip‑level or IP‑level timing closure
• Deep working knowledge of PrimeTime, PTECO, and distributed multi‑scenario analysis tools
• Proven experience closing timing on high performance designs, ideally memory IP such as DDR, LPDDR, or HBM
• Strong scripting skills in Python, Tcl, Perl, or shell for automation and flow development
• Solid understanding of timing constraints, asynchronous timing analysis, and multi‑corner/multi‑mode closure strategies
• Experience with physical design flows and RTL2GDS implementation is a strong plus

Who You Are

• You can look at a timing report with 500 violations and know within ten minutes which five actually matter and which are noise
• You push back when a constraint does not make sense or when an ECO will create more problems than it solves, and you do it with data, not opinion
• You write scripts that other engineers actually use because you think about maintainability and clarity, not just getting it done once
• You communicate timing issues to physical design teams and RTL engineers in terms they understand, without losing the technical nuance that matters for the fix
• You stay organized across multiple IPs, multiple corners, and multiple release schedules without dropping threads or missing deadlines
• You are comfortable working with global teams across time zones, and you know how to make asynchronous collaboration actually work

The Team You'll Be Part Of

You will join the IP Group working on Interface PHYs. This team focuses on timing closure and physical design for high performance interface IP that connects memory and SoC components across Synopsys product lines. The work is technical, the standards are high, and the IP you help close will ship in customer silicon around the world.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.