Physical ASIC Design Implementation Engineer

ENGIBEX; Vlaams-Brabant; On-site; EUR 60,000 - 90,000; Full time

Job summary

Engibex is seeking an IC/SoC design consultant in Belgium to drive the Cadence Innovus Place & Route flow and lead timing budget partitioning for sub-blocks. You will work directly with the Physical Design team to achieve tape-out sign-off and communicate technical specifications to customers.

The role emphasizes setting up flows for chosen libraries, implementing low-power UPF strategies, and ensuring robust timing and physical verification.

Qualifications

• Experience setting up flow for library sets and foundry node.
• Experience in low power design (UPF) and debug SDC.
• Knowledge in floorplanning and power grid design for top level and blocks.
• Place, CTS and routing skills.
• Solve setup and hold violations and sign-off extraction/timing.
• Experience in physical verification and logic equivalence checks.

Responsibilities

• Direct contact with customers for future projects.
• Lead partitioning and split top-level SDC into timing budgets.
• Collaborate with Physical Design to drive signoff closure for tape-out.
• Communicate customer specifications as a technical voice.

Skills

Cadence Innovus

Floorplanning

Place & Route

Power integrity

Timing analysis

Sign-off experience

SPEF/QUANTUS timing

Tools

Tempus

Voltus

SPEF/QUANTUS

DRC/ERC/LVS

Job description

We are a Belgian engineering consulting firm that assists SMEs and large industrial organizations in bringing their innovation and R&D initiatives to life.

Job Description

• Direct contact with our customers for future projects.
• Full understanding of the complete Cadence Innovus Place&Route flow.
• Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
• Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
• Technical voice to the customer to discuss his specifications.

Profile / Requirements

• Experience in setting-up the flow for the specific library set and foundry node used
• Experience in setting-up low power design (UPF) and debug sdc file
• Knowledge in Floorplanning & power grid design for toplevel aswell as blocks
• Place, CTS & Routing
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check

Why join us ?

We offer you a position as a consultant within the fascinating world of high tech and innovation. We provide a complete package with on one side training, coaching and a close follow-up, and on the other side a balanced salary package with fringe benefits based on your capabilities and experience.

Working with us means choosing a long-term perspective, development possibilities, and a personal approach. A human-centered, diverse company that values and supports your physical and mental well-being.