Application Specific Integrated Circuit Engineer

Vivid Resourcing Ltd; Vlaams-Brabant; On-site; EUR 65,000 - 90,000; Full time

Job summary

Vivid Resourcing Ltd in Leuven is recruiting an ASIC Engineer to join a multidisciplinary semiconductor team. You will verify and develop complex SoCs, IPs and subsystems, spanning analogue and digital domains, with hands-on simulation, debugging and methodology development.

You will own critical verification activities, contribute to team methodologies and mentor junior engineers, collaborating across design teams to ensure robust implementation and validation of designs.

Qualifications

• Proven experience in ASIC design, verification or mixed-signal verification.
• Strong understanding of digital and analogue design principles.
• Hands-on experience with simulation, verification and debugging of complex IC designs.
• Strong knowledge of SystemVerilog and UVM.
• Experience with behavioural modelling languages such as Verilog-A, Verilog-AMS, SV-RNM or VHDL-AMS.
• Experience with SPICE and digital simulation environments.
• Good knowledge of EDA tools such as Cadence and/or Synopsys.
• Experience developing verification environments, testbenches and simulation flows.
• Programming or scripting experience with Python, Perl, TCL or similar.
• Strong analytical and problem-solving skills, particularly when debugging complex design issues.
• Comfortable working across analogue and digital engineering teams.
• Strong communication skills and the ability to work collaboratively within a technical team.

Responsibilities

• Develop and improve simulation and verification methodologies and flows.
• Review technical specifications and develop verification plans.
• Manage BOMs, netlists and associated verification setups.
• Work closely with analogue and digital design teams to track design changes and updates.
• Run and debug SPICE-based and digital simulations for SoCs, IPs and subsystems.
• Review simulation environments and ensure appropriate test conditions are being applied.
• Analyse simulation results and waveforms to identify functional issues and determine root causes.
• Develop behavioural models using Verilog-A/AMS, SV-RNM and/or VHDL-AMS.
• Develop and optimise testbenches using tools such as Cadence Xcelium, Virtuoso and Synopsys platforms.
• Contribute to regression, automation and verification infrastructure improvements.
• Develop scripts for tasks such as simulation management, log parsing and result analysis.
• Document verification results, debug findings and methodology updates.
• Take ownership of critical technical tasks and support the planning and distribution of work within the team.
• Provide technical guidance, mentoring and knowledge sharing to other engineers.

Skills

ASIC design

Verification

SystemVerilog

UVM

Verilog-A/AMS

Verilog-AMS

SV-RNM

VHDL-AMS

SPICE

Python

Perl

TCL

Debugging

Communication

Tools

Cadence Xcelium

Virtuoso

Synopsys platforms

Job description

We're currently recruiting for an ASIC Engineer to join a multidisciplinary semiconductor development team in Leuven.

You will be involved in the verification and development of complex SoCs, IPs and subsystems, working across both analogue and digital domains.

The role combines hands-on simulation, verification and debugging with the development of verification methodologies, behavioural models and automation. You will work closely with analogue and digital design teams to understand design intent, identify issues and ensure robust implementation and validation of the final design.

You will also have the opportunity to take ownership of critical technical activities, contribute to the development of team methodologies and provide guidance to less experienced engineers.

Key Responsibilities:

• Develop and improve simulation and verification methodologies and flows.
• Review technical specifications and develop verification plans.
• Manage BOMs, netlists and associated verification setups.
• Work closely with analogue and digital design teams to track design changes and updates.
• Run and debug SPICE-based and digital simulations for SoCs, IPs and subsystems.
• Review simulation environments and ensure appropriate test conditions are being applied.
• Analyse simulation results and waveforms to identify functional issues and determine root causes.
• Develop behavioural models using Verilog-A/AMS, SV-RNM and/or VHDL-AMS.
• Develop and optimise testbenches using tools such as Cadence Xcelium, Virtuoso and Synopsys platforms.
• Contribute to regression, automation and verification infrastructure improvements.
• Develop scripts for tasks such as simulation management, log parsing and result analysis.
• Document verification results, debug findings and methodology updates.
• Take ownership of critical technical tasks and support the planning and distribution of work within the team.
• Provide technical guidance, mentoring and knowledge sharing to other engineers.

Your Profile:

• Proven experience in ASIC design, verification or mixed-signal verification.
• Strong understanding of digital and analogue design principles.
• Hands-on experience with simulation, verification and debugging of complex IC designs.
• Strong knowledge of SystemVerilog and UVM.
• Experience with behavioural modelling languages such as Verilog-A, Verilog-AMS, SV-RNM or VHDL-AMS.
• Experience with SPICE and digital simulation environments.
• Good knowledge of EDA tools such as Cadence and/or Synopsys.
• Experience developing verification environments, testbenches and simulation flows.
• Programming or scripting experience with Python, Perl, TCL or similar.
• Strong analytical and problem-solving skills, particularly when debugging complex design issues.
• Comfortable working across analogue and digital engineering teams.
• Strong communication skills and the ability to work collaboratively within a technical team.

The Offer:

• A salary & benefits package commensurate with experience