Principal ASIC Physical Design Lead (RTL to GDSII)

Nalys Group

Vlaams-Brabant

On-site

EUR 120,000 - 180,000

Full time

7 days ago
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Job summary

Nalys Group is seeking a Principal Physical Design Engineer for a major semiconductor client in Belgium. You will own the physical implementation from RTL to GDSII, focusing on floor planning, placing and routing, clock tree synthesis, and STA, while driving low-power strategies and automation improvements.

You will mentor engineers, lead design methodologies, and collaborate with cross-functional teams to ensure high-quality outcomes for next-generation SoC and IP blocks.

Qualifications

  • Minimum 15 years of ASIC physical design experience.
  • Proven tape-out experience on advanced process nodes.
  • Strong scripting in Tcl/Perl/Python to automate flows.
  • Deep knowledge of DFM and STA constraints.
  • Leadership and mentoring capabilities.

Responsibilities

  • Own the physical implementation—from RTL to GDSII.
  • Lead floorplanning, placement, routing, clock tree synthesis, and STA.
  • Develop low-power strategies including gating and multi-voltage designs.
  • Drive tooling and methodologies to boost efficiency.
  • Collaborate with architecture and verification teams and mentor engineers.

Skills

ASIC physical design
Floor planning
Place & route
Clock tree synthesis
Static timing analysis
Scripting: Tcl/Perl/Python
Mentoring
Team leadership
Power/DFM

Education

Bachelor's or Master's in Electrical/Electronics

Tools

Cadence Innovus/Tempus
Synopsys Fusion Compiler/PrimeTime
Ansys RedHawk/PathFinder

Job description

Nalys Group is seeking a Principal Physical Design Engineer for a major semiconductor client in Belgium. You will own the physical implementation from RTL to GDSII, focusing on floor planning, placing and routing, clock tree synthesis, and STA, while driving low-power strategies and automation improvements.

You will mentor engineers, lead design methodologies, and collaborate with cross-functional teams to ensure high-quality outcomes for next-generation SoC and IP blocks.

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