Lead Physical ASIC Design Engineer (12–5nm)

imec; Vlaams-Brabant; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

imec is seeking a highly experienced Physical ASIC design engineer to join the DSRD Back-End group in Leuven. You will work directly with customers, mastering the Cadence Innovus Place&Route flow across library and foundry nodes.

Responsibilities include floorplanning, power integrity, timing, and sign-off tasks to ensure successful tape-outs. We value a Master in Electronics and 8+ years in physical implementation for advanced nodes, with English fluency and strong debugging skills to

Qualifications

• Master Degree in Electronics is required.
• Excellent communication skills in English and ability to work in an international team.
• 8+ years of experience in physical implementation of advanced nodes (12–5nm).
• Experience debugging tool/flow/design issues.

Responsabilités

• Set up Cadence Innovus Place&Route flow for library and node.
• Perform floorplanning, power grid design and clock tree synthesis.
• Manage sign-off processes to ensure tape-out readiness.
• Collaborate with customers and internal teams to discuss specifications.

Connaissances

Communication skills

Debugging

Cadence Innovus

Sign-off tools

Formation

Master Degree in Electronics

Outils

Cadence Innovus

Sign-off tools (TEMPUS/VOLTUS/SPEF)

Description du poste

imec is seeking a highly experienced Physical ASIC design engineer to join the DSRD Back-End group in Leuven. You will work directly with customers, mastering the Cadence Innovus Place&Route flow across library and foundry nodes.

Responsibilities include floorplanning, power integrity, timing, and sign-off tasks to ensure successful tape-outs. We value a Master in Electronics and 8+ years in physical implementation for advanced nodes, with English fluency and strong debugging skills to