Physical ASIC Design Implementation Engineer

Engibex; Vlaams-Brabant; On-site; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Training and coaching

Fringe benefits

Job summary

Engibex in Belgium seeks a Physical Implementation Engineer to lead backend flows for full chips, from netlist-in to GDSII-out, across nodes from N2 to 180nm, leveraging Cadence Innovus Place&Route.

You will directly engage with customers, partition top levels, and drive sign-off with the Physical Design team through tape-out, ensuring timing, power, and verification requirements are met.

Qualifications

• Experience setting up the flow for the library set and foundry node used.
• Experience with UPF low power design and debug sdc files.
• Knowledge of floorplanning and power grid design for top level and blocks.
• Proficient with Place, CTS and Routing.
• Ability to resolve setup and hold violations.
• Sign-off extraction (SPEF/QUANTUS), timing (TEMPUS), power analysis (VOLTUS).
• Physical verification (DRC, LVS, ERC, ANT) and logic equivalence checks.

Responsibilities

• Direct contact with customers for upcoming projects.
• Fully understand Cadence Innovus Place&Route flow.
• Lead partitioning and split top level SDC into timing budgets for sub-blocks.
• Collaborate with Physical Design team to drive sign-off for tape-out.
• Be the technical voice to discuss customer specifications.

Skills

Library flow setup

UPF / low power design

Floorplanning

Place & Routing

Setup/hold violations

Timing sign-off (TEMPUS)

Power analysis (VOLTUS)

Physical verification (DRC/LVS/ERC/ANT

Tools

Cadence Innovus

TEMPUS

VOLTUS

SPEF/QUANTUS

Job description

We are a Belgian engineering consulting firm that assists SMEs and large industrial organizations in bringing their innovation and R&D initiatives to life.

Job Description

Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow.

• Direct contact with our customers for future projects.
• Full understanding of the complete Cadence Innovus Place&Route flow.
• Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
• Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
• Technical voice to the customer to discuss his specifications

Profile / Requirements

• Experience in setting-up the flow for the specific library set and foundry node used
• Experience in setting-up low power design (UPF) and debug sdc file
• Knowledge in Floorplanning & power grid design for toplevel aswell as blocks
• Place, CTS & Routing
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check

Why join us ?

We offer you a position as a consultant within the fascinating world of high tech and innovation. We provide a complete package with on one side training, coaching and a close follow-up, and on the other side a balanced salary package with fringe benefits based on your capabilities and experience.

Working with us means choosing a long-term perspective, development possibilities, and a personal approach. A human-centered, diverse company that values and supports your physical and mental well-being.