Physical ASIC Design Implementation Engineer

imec; Vlaams-Brabant; On-site; EUR 90,000 - 120,000; Full time

Job summary

imec is seeking a highly experienced Physical ASIC design engineer to join the DSRD Back-End group in Leuven. You will work directly with customers, mastering the Cadence Innovus Place&Route flow across library and foundry nodes.

Responsibilities include floorplanning, power integrity, timing, and sign-off tasks to ensure successful tape-outs. We value a Master in Electronics and 8+ years in physical implementation for advanced nodes, with English fluency and strong debugging skills to

Qualifications

• Master Degree in Electronics is required.
• Excellent communication skills in English and ability to work in an international team.
• 8+ years of experience in physical implementation of advanced nodes (12–5nm).
• Experience debugging tool/flow/design issues.

Responsibilities

• Set up Cadence Innovus Place&Route flow for library and node.
• Perform floorplanning, power grid design and clock tree synthesis.
• Manage sign-off processes to ensure tape-out readiness.
• Collaborate with customers and internal teams to discuss specifications.

Skills

Communication skills

Debugging

Cadence Innovus

Sign-off tools

Education

Master Degree in Electronics

Tools

Cadence Innovus

Sign-off tools (TEMPUS/VOLTUS/SPEF)

Job description

As Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus Place&Route flow.

What you will do

For more than 25 years, imec has been offering an ASIC prototyping and production service to worldwide companies. Imec helps its customers to design their integrated circuits (chips) and bring them from the prototype to the production stage. Our list of customers includes more than 900 universities and companies worldwide. For the further extension of the physical digital implementation group (Back-End group) in DSRD, we are looking for a highly motivated engineer.

DSRD, as part of imec, has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. This unit supports worldwide customers in the layout, prototype, fabrication and test of advanced electronic products.

As Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus Place&Route flow:

• Set up the flow for the specific library set and foundry node used
• Set up low power design (UPF)
• Floorplanning & power grid design
• Detailed Timing Driven Placement
• Clock Tree Synthesis
• Scan chain re-stitching
• Detailed Timing Driven Route (incl. SI)
• IPO’s (in-place optimization) to get the timing in all corners correct
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS)
• Sign-off timing (TEMPUS)
• Sign-off Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT)
• Logic equivalent check

For hierarchical designs you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out, You are also the technical voice to the customer to discuss his specifications.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its office in Leuven. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You have a Master Degree in Electronics
• You have at least 8 years of experience in physical implementation in advanced nodes (12 – 5nm) and hierarchical designs.
• You have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains.
• You have experience in debugging any tool/flow/design issue.
• You have excellent communication skills (English is a must) and can work within an international team.
• You like to interact with customers.

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee-based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.