Senior DFT Architect for Next-Gen SoCs

EURAXESS Czech Republic; Belgique; À distance; EUR 90 000 - 120 000; Plein temps

Résumé du poste

IMEC in Leuven, Belgium, is seeking a Senior DFT Engineer to advance Design-for-Test capabilities for next-generation semiconductor devices. You will shape test strategies for complex SOCs, coordinate with project teams, and drive DFT implementation across advanced nodes.

The role emphasizes collaboration with physical design and test teams, ensuring fault coverage and high-quality silicon testability. 40 hours/week, permanent position in a world-leading R&D environment.

Qualifications

• Experience with DFT insertion and ATPG.
• Knowledge of boundary scan, MBIST/repair, OPCG/OCC.
• Fluency with Verilog/VHDL for test logic.
• Familiarity with IEEE 1149.1/1149.6/1687 (IJTAG).
• Proficient with EDA tools such as Tessent; Genus/Modus.

Responsabilités

• Architect DFT solutions for SOCs and multi-block designs.
• Coordinate DFT requirements with project teams and customers.
• Define timing constraints for DFT test-modes.
• Insert and validate DFT techniques on SOCs and subsystems.
• Collaborate with physical design and test engineering teams.

Description du poste

IMEC in Leuven, Belgium, is seeking a Senior DFT Engineer to advance Design-for-Test capabilities for next-generation semiconductor devices. You will shape test strategies for complex SOCs, coordinate with project teams, and drive DFT implementation across advanced nodes.

The role emphasizes collaboration with physical design and test teams, ensuring fault coverage and high-quality silicon testability. 40 hours/week, permanent position in a world-leading R&D environment.