Physical Design Engineer

IC Resources; Antwerpen; On-site; EUR 70,000 - 110,000; Full time

Job summary

IC Resources is seeking a Physical Design Engineer in Antwerp, Belgium to drive the RTL-to-GDS backend flow and optimize digital designs for advanced imaging tech. The role covers implementation, optimization and backend methodology development in close collaboration with analog and digital teams.

The ideal candidate has hands-on experience with the complete digital backend flow, Cadence and other EDA tools, and scripting in Tcl/Python. A strong microelectronics background is essential.

Qualifications

• Bachelor’s degree or above in microelectronics or related field.
• Experience with the complete digital backend flow from RTL to GDS.
• Experience with industry-standard EDA tools.
• Proficiency in scripting languages (Tcl, Python).
• Experience with Cadence tools is preferred.

Responsibilities

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning and CTS.
• Provide innovative solutions to reach product targets and optimize performance, power and area.
• Develop, maintain and enhance backend methodologies, flows and automation scripts.
• Collaborate with analog team and digital design and verification engineers to resolve implementation challenges.
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective.

Skills

Digital backend flow

EDA tools

Scripting Tcl/Python

Cadence tools

Education

Bachelor's degree in microelectronics

Tools

Cadence tools

Job description

This client is looking for a Physical Design Engineer to join their semiconductor R&D team in Antwerp, working on the implementation of complex digital circuitry for advanced imaging technologies.

This is a hands-on Physical Design Engineer position covering the RTL-to-GDS flow, with scope to work across implementation, optimisation and backend methodology development.

Key responsibilities:

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and logic equivalence checking (LEC).
• Provide innovative solutions to reach product targets and drive performance, power and area optimizations.
• Develop, maintain and enhance backend methodologies, flows and automation scripts.
• Collaborate closely with the analog team and the digital design and verification engineers to resolve implementation challenges and successfully complete the project.
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective.

Position Qualifications

• Bachelor’s degree or above in microelectronics or related fields.
• Experience with the complete digital backend flow from RTL to GDS.
• Experience with industry-standard EDA tools.
• Proficiency in scripting languages (Tcl, Python).
• Experience with Cadence tools is preferred