Senior DFT Engineer: Lead 5nm SOC Test Innovation

Unist; Belgique; À distance; EUR 90 000 - 130 000; Plein temps

Résumé du poste

imec in Leuven, Belgium, is seeking a Senior DFT Engineer to shape next‑gen semiconductors through Design‑for‑Test innovation. You will lead DFT insertion for SOCs, define constraints, and collaborate with physical design and test teams to ensure testability and performance of complex chip designs.

The role requires 5+ years in DFT, experience with boundary scan, MBIST, ATPG, and IEEE 1149.x standards; hands-on with Tessent tools and TCL scripting.

Qualifications

• 5+ years of experience with DFT insertion and ATPG.
• Strong knowledge of boundary scan, MBIST/repair, OPCG/OCC and test pattern generation.
• Experience with DFT integration of complex PHY blocks (PCIe/UCIe/LPDDR5).
• Hands-on scripting with TCL for DFT workflows.
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG).
• Experience with Tessent tools and related verification.

Responsabilités

• Architect DFT solutions for SOCs with complex IPs and large-scale designs.
• Coordinate DFT requirements with project teams and customers.
• Implement, validate, and optimize DFT techniques on SOCs and subsystems.
• Define timing constraints for DFT test-modes and ensure fault coverage.

Connaissances

DFT insertion

ATPG

Verilog/VHDL

IEEE 1149.1/1149.6/1687

Tessent

Tessent SSN

TCL scripting

SOC testability

EDA tools

DFT flows

Outils

Tessent (Siemens)

Genus/Modus (Cadence)

Description du poste

imec in Leuven, Belgium, is seeking a Senior DFT Engineer to shape next‑gen semiconductors through Design‑for‑Test innovation. You will lead DFT insertion for SOCs, define constraints, and collaborate with physical design and test teams to ensure testability and performance of complex chip designs.

The role requires 5+ years in DFT, experience with boundary scan, MBIST, ATPG, and IEEE 1149.x standards; hands-on with Tessent tools and TCL scripting.