Senior Custom Analog Layout Engineer - RF/PLL Lead

imec; Vlaams-Brabant; Vor Ort; EUR 65.000 - 90.000; Vollzeit

Zusammenfassung

imec in Leuven, Belgium, seeks a Full Custom Analog Layout Engineer to join the Design Services Custom Layout team. You will design analog layouts for advanced analog, mixed-signal, and RF circuits across the ASIC lifecycle, from design to tape-out, ensuring performance and manufacturability.

You will perform physical verifications (DRC/LVS/EM/IR), floorplanning, top-level routing, and chip-level sign-offs, while contributing to guidelines and documentation for multiple technology nodes.

Qualifikationen

• Master’s degree in Electronics or Electrical Engineering.
• Experience designing analog blocks and top-level integration.
• Knowledge of FINFETs and advanced nodes is a plus.
• Sound knowledge of EDA tools.
• Understanding of Layout Dependent Effects for deep submicron nodes.
• Tape-out experience in advanced process technology nodes is preferred.
• Knowledge about Radiation Hardening and its implementation in Layouts.
• Familiarity with versioning tools (svn, cliosoft, etc.).

Aufgaben

• Design Analog Layouts like PLL, BG, LVDS, IVREF for Space and research projects.
• Perform DRC, LVS, EM/IR and other checks for designed blocks.
• Conduct floorplanning and top-level routing across power domains.
• Complete CHIP level validations after Dummy fill and sign-off checks.
• Deliver all outputs in time to meet project deadlines.
• Archive reports and checklists at project end.
• Contribute layout guidelines, checklists, and documents for technology nodes.

Kenntnisse

Analog layout design

Top-level integration

EDA tools

Layout Dependent Effects

Radiation hardening

Versioning tools

Ausbildung

Master's degree in Electronics or Electrical Engineering

Tools

svn

Jobbeschreibung

imec in Leuven, Belgium, seeks a Full Custom Analog Layout Engineer to join the Design Services Custom Layout team. You will design analog layouts for advanced analog, mixed-signal, and RF circuits across the ASIC lifecycle, from design to tape-out, ensuring performance and manufacturability.

You will perform physical verifications (DRC/LVS/EM/IR), floorplanning, top-level routing, and chip-level sign-offs, while contributing to guidelines and documentation for multiple technology nodes.