Full Custom ASIC Analog Layout Engineer

imec; Vlaams-Brabant; In loco; EUR 65.000 - 90.000; Tempo pieno

Descrizione del lavoro

imec in Leuven, Belgium, seeks a Full Custom Analog Layout Engineer to join the Design Services Custom Layout team. You will design analog layouts for advanced analog, mixed-signal, and RF circuits across the ASIC lifecycle, from design to tape-out, ensuring performance and manufacturability.

You will perform physical verifications (DRC/LVS/EM/IR), floorplanning, top-level routing, and chip-level sign-offs, while contributing to guidelines and documentation for multiple technology nodes.

Competenze

• Master’s degree in Electronics or Electrical Engineering.
• Experience designing analog blocks and top-level integration.
• Knowledge of FINFETs and advanced nodes is a plus.
• Sound knowledge of EDA tools.
• Understanding of Layout Dependent Effects for deep submicron nodes.
• Tape-out experience in advanced process technology nodes is preferred.
• Knowledge about Radiation Hardening and its implementation in Layouts.
• Familiarity with versioning tools (svn, cliosoft, etc.).

Mansioni

• Design Analog Layouts like PLL, BG, LVDS, IVREF for Space and research projects.
• Perform DRC, LVS, EM/IR and other checks for designed blocks.
• Conduct floorplanning and top-level routing across power domains.
• Complete CHIP level validations after Dummy fill and sign-off checks.
• Deliver all outputs in time to meet project deadlines.
• Archive reports and checklists at project end.
• Contribute layout guidelines, checklists, and documents for technology nodes.

Conoscenze

Analog layout design

Top-level integration

EDA tools

Layout Dependent Effects

Radiation hardening

Versioning tools

Formazione

Master's degree in Electronics or Electrical Engineering

Strumenti

svn

Descrizione del lavoro

Join imec and transform cutting-edge analog innovation into silicon for a smarter, connected future.

Who we are

As Full Custom Analog Layout Engineer, you join the Design Services Custom Layout team. This team specializes in full-custom IC layout for advanced analog, mixed-signal, and RF circuits. We support customers and internal programs across the complete ASIC development lifecycle, from design implementation and layout optimization to verification and tape-out, ensuring high performance, manufacturability, and compliance with advanced process technologies.

What you will do

• Design Analog Layouts like PLL, BG, LVDS, IVREF etc. for various projects for Space Application and various other Research projects at Imec.
• Perform physical verifications like DRC, LVS, EM/IR and other applicable checks for the designed blocks.
• Perform floorplan and top-level routing, keeping in mind the various power domains, and various challenges associated with mixed signal design.
• Perform all CHIP level validations post Dummy fill and other sign-off checks necessary for the tape-out.
• Provide all the deliverables in time to meet the Project deadlines.
• Archival of all the reports and checklists at the end of the Project.
• Contribute various Layout guidelines, checklists and other documents for various Technology nodes.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You have a master’s degree (or equivalent through experience) in Electronics or Electrical Engineering.
• You have experience in designing various Analog Blocks and for Top Level integration of these blocks and signoff checks.
• Knowledge to design layouts in FINFETs and other advanced SOI nodes will be an added advantage.
• You must have sound knowledge of EDA Tools.
• Understanding of Layout Dependent Effects for deep submicron technology nodes.
• Tape-out experience in advanced process technology nodes is preferable.
• Knowledge about Radiation Hardening and its implementation in Layouts.
• Knowledge about svn, cliosoft or any other versioning tools.