UVM Digital Verification Engineer - FPGA/ASIC

Inuplands; Cambridge (MA); On-site; USD 75,000 - 150,000; Full time

Benefits offered by this job

Work-life balance programs

Employee clubs

Health and finance workshops

Job summary

A leading research and development firm in Cambridge, MA is seeking an experienced UVM Digital Verification Engineer to innovate digital and mixed-signal designs. The role involves designing circuits, developing verification plans, and contributes to complex hardware solutions. The ideal candidate has a degree in Engineering, strong skills in System Verilog and UVM, and experience with integrated circuits. The position offers competitive compensation and the opportunity to work in a collaborative team environment.

Qualifications

• Requires 3-5 years experience with bachelor's, or 0-2 years with master's in ASIC Hardware Engineering.
• Proficiency in modern verification strategies.
• Familiarity with DDR3/DDR4, Amba Axi protocols.

Responsibilities

• Design and simulate circuits at transistor-level.
• Contribute to complex chip architectures.
• Develop verification and test plans.
• Mentor junior engineers in the group.

Skills

Integrated circuit design

Communication skills

Analytical skills

Problem-solving skills

Time management

Education

Bachelor's degree in Engineering or related field

Master's degree preferred

Tools

System Verilog

Python

UVM

Questasim

VCS

Job description

A leading research and development firm in Cambridge, MA is seeking an experienced UVM Digital Verification Engineer to innovate digital and mixed-signal designs. The role involves designing circuits, developing verification plans, and contributes to complex hardware solutions. The ideal candidate has a degree in Engineering, strong skills in System Verilog and UVM, and experience with integrated circuits. The position offers competitive compensation and the opportunity to work in a collaborative team environment.