FPGA Verification Engineer: UVM, SystemVerilog & Debugging

Compunnel, Inc.; Mountain View (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced methodologies and requires strong expertise in SystemVerilog, UVM, and debugging skills. The ideal candidate will develop verification plans, utilize industry-standard tools, and collaborate with cross-functional teams to enhance product quality. Competitive compensation is offered.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog, UVM, and scripting languages (Python, Perl).
• Experience with hardware description languages such as VHDL and Verilog.
• Excellent debugging, analytical, and problem-solving skills.

Responsibilities

• Develop and execute verification plans using SystemVerilog and UVM.
• Utilize standard verification tools for simulation and analysis.
• Perform code coverage and functional coverage analysis.
• Debug and resolve design and verification issues efficiently.
• Document verification processes and results.

Skills

SystemVerilog

UVM

Debugging skills

Problem-solving skills

Analytical skills

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

QuestaSim

Synopsys VCS

EDA tools from Cadence

Job description

A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced methodologies and requires strong expertise in SystemVerilog, UVM, and debugging skills. The ideal candidate will develop verification plans, utilize industry-standard tools, and collaborate with cross-functional teams to enhance product quality. Competitive compensation is offered.