Senior Mixed-Signal Verification Engineer (UVM)

Cirrus Logic; Chandler (AZ); On-site; USD 100,000 - 145,000; Full time

Job summary

A prominent silicon technology company in Arizona seeks an experienced Design Verification Engineer to join its team. This role involves collaborating with digital and analog designers to ensure high-quality mixed-signal IC solutions. Candidates should have a Bachelor’s, Master’s, or PhD in Electrical Engineering or related fields, with relevant experience in ASIC verification and HDLs like Verilog and SystemVerilog. The position offers a rigorous working environment with opportunities to advance verification methodologies.

Qualifications

• 5+ years of experience in relevant roles, or 3+ years with a Master’s, or none required with a PhD.
• Experience in silicon design and/or ASIC verification is essential.
• Hands-on experience with testbench architecture and stimulus generation required.

Responsibilities

• Develop comprehensive verification plans based on design requirements.
• Perform functional verification at block and chip level.
• Design and implement UVM-based testbenches and maintain them.

Skills

Verilog

SystemVerilog with UVM

Digital design principles

ASIC verification

Testbench architecture

Coverage analysis

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related

Master’s degree

PhD

Tools

Regression execution tools

Mixed-signal ASIC verification tools

Job description

A prominent silicon technology company in Arizona seeks an experienced Design Verification Engineer to join its team. This role involves collaborating with digital and analog designers to ensure high-quality mixed-signal IC solutions. Candidates should have a Bachelor’s, Master’s, or PhD in Electrical Engineering or related fields, with relevant experience in ASIC verification and HDLs like Verilog and SystemVerilog. The position offers a rigorous working environment with opportunities to advance verification methodologies.