FPGA Verification Engineer | UVM/SystemVerilog Expert

Allps GmbH; Santa Clara (CA); On-site; USD 206,309,376; Full time

Job summary

A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating closely with design engineers and ensuring product quality. The ideal candidate will have over 8 years of experience in FPGA and strong proficiency in UVM and SystemVerilog. This is a full-time onsite role, requiring a Bachelor's or Master's degree in Electrical or Computer Engineering. Competitive rate offered with 5 days onsite per week.

Qualifications

• 8+ years in FPGA design.
• 5+ years of experience in UVM.
• 5+ years of experience in SystemVerilog.
• 3+ years of experience in FPGA verification.

Responsibilities

• Develop and execute verification plans for FPGA designs.
• Create and maintain test benches using UVM and SystemVerilog.
• Document verification results and provide reports.
• Participate in design reviews and contribute to verification strategy.

Skills

FPGA

UVM

SystemVerilog

Debugging

Collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in a related field

Tools

QuestaSim

Synopsys VCS

Job description

A leading engineering company is seeking a highly skilled FPGA Verification Engineer in Santa Clara, CA. You will verify complex FPGA designs, collaborating closely with design engineers and ensuring product quality. The ideal candidate will have over 8 years of experience in FPGA and strong proficiency in UVM and SystemVerilog. This is a full-time onsite role, requiring a Bachelor's or Master's degree in Electrical or Computer Engineering. Competitive rate offered with 5 days onsite per week.