Design Verification Engineer

EDA CAREERS, (Technology Futures Inc).; San Francisco (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite team, you will develop and deploy UVM testbenches, collaborating closely with machine learning and software engineers. This position is perfect for those eager to explore AI-integrated semiconductor design and make a significant impact in the industry. Join a mission-driven team that is reshaping the future of chip verification and development.

Qualifications

• Proven ability to architect UVM environments and debug simulations.
• Deep knowledge of verification strategies and coverage-driven development.
• Practical experience with EDA tools and proficiency in scripting.

Responsibilities

• Build and optimize UVM-based testbenches integrated with AI workflows.
• Collaborate with ML and software teams to improve verification artifacts.
• Support verification best practices and engage with customer projects.

Skills

UVM

EDA tools

VLSI front-end design

Python scripting

Verification strategies

Constrained-random testing

Communication skills

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Siemens

Job description

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from EDA CAREERS, (Technology Futures Inc).

President at EDA-CAREERS and TECHNOLOGY FUTURES Inc.

YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors!

PLEASE HAVE EDA/SEMICONDUCTOR EXPERIENCE WHEN APPLYING!

My client is a promising, innovative, well-funded startup backed by top-tier investors and trusted by major chip design companies and AI chip startups. They operate at the cutting edge of AI and semiconductor design. They are seeking an experienced Design Verification Engineer with expertise in UVM.

Their focus is on building verification platforms using LLMs to automate and accelerate chip development. The team comprises experts in AI, software development, and semiconductor design. Their platform is deployed across Fortune 100 companies and leading design teams. You will join a small, elite team solving complex chip verification challenges by integrating traditional methods with generative AI.

Their mission is to significantly accelerate silicon development, reducing costs, time, and engineering efforts for top chip teams. Their customers include Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI, along with over ten innovative startups. Their backers include Khosla Ventures, Cerberus, and Clear Ventures. The founders have impressive backgrounds, making this a promising venture.

Job Description:

They seek skilled Verification Engineers or Chip Designers with substantial experience in VLSI front-end design flows, especially UVM, to work closely with ML and software teams. In this role, you will apply LLMs for DV, working on advanced technologies that blend your verification expertise with ML for innovative chip design solutions. You will learn from experienced ML leads and contribute directly to customer projects.

This role is ideal for a chip designer eager to explore AI-integrated semiconductor design. It offers a chance to make a significant impact by pioneering this new approach to chip design.

Your Role:

As a UVM Specialist, you will develop, refine, and deploy UVM testbenches within an AI-enhanced verification environment. You will collaborate with ML and software engineers to guide LLMs in automating the DV process, support customer deployments, and shape the future of chip verification.

Key Responsibilities:

• Build and optimize UVM-based testbenches integrated with AI workflows.
• Collaborate with ML and software teams to improve verification artifacts like test plans, monitors, and coverage models generated by LLMs.
• Support verification best practices and AI-driven code generation and debugging automation.
• Work directly with customers to understand their DV needs and deploy innovative solutions.
• Contribute to internal test suites, benchmarks, and AI model feedback loops.
• Stay updated on DV methodologies and AI advancements in hardware design.
• Engage with customer projects to develop practical, innovative solutions.

Qualifications:

• Proven ability to architect UVM environments from scratch, debug simulations, and achieve close coverage.
• Deep knowledge of verification strategies, assertions, constrained-random testing, and coverage-driven development.
• Practical experience with EDA tools (Synopsys, Cadence, Siemens).
• Proficiency in scripting and automation (Python, etc.).
• Familiarity with formal verification and interest in LLMs or AI workflows is a strong plus.
• Excellent communication and collaboration skills, including customer-facing work.
• Bachelor’s or Master’s degree in EE, CE, or related fields.
• To learn more, contact Mark Gilbert via email at [e-mail] or call 305-598-2222x3. Please include your resume for a more detailed discussion.

Additional Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job functions: IT, Engineering, QA
• Industries: Semiconductor, Hardware, Electronics