Senior UVM Digital Verification Engineer - FPGA/ASIC

Draper; Boston (MA); On-site; USD 82,300 - 220,000; Full time

Benefits offered by this job

Work-life balance programs

Employee clubs (photography, yoga)

Discounts to local museums and culture

Job summary

Draper’s Digital Design Team seeks a Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation and communications.

You will develop verification approaches, author verification plans, and work with multi-disciplinary teams, RTL designers, and external partners to deliver robust digital

Qualifications

• Requires 5-7 years experience in systems analysis or related.
• Experience in integrating descriptive modeling tools with other simulation tools.

Responsibilities

• Develop verification approaches and verification plans.
• Author and execute verification plans and use formal analysis tools.
• Work in multi-disciplinary teams with opportunities to learn and contribute to projects.
• Develop UVM Agents for proprietary buses and instantiate VIPs for industry standard buses.
• Collaborate with RTL designers to resolve simulation issues and achieve 100% code coverage.
• Mentor junior engineers and provide constructive feedback.

Skills

SystemVerilog

UVM/UVMF

Python scripting

Digital verification

FPGA/ASIC verification

Mathematical analysis

Leadership / mentoring

Linux environment

Education

Bachelor’s degree in Aerospace, Electrical, Mechanical, or other relevant Engineering field

Master’s degree preferred

Tools

QuestaSim

Xcelium

VCS

VIP development

DDR3/DDR4

Job description

Draper’s Digital Design Team seeks a Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation and communications.

You will develop verification approaches, author verification plans, and work with multi-disciplinary teams, RTL designers, and external partners to deliver robust digital