UVM Digital Verification Engineer - FPGA/ASIC

Draper Inc.; Cambridge (MA); On-site; USD 75,000 - 150,000; Full time

Benefits offered by this job

Workplace flexibility

Employee clubs

Health and finance workshops

Discounts to local museums

Job summary

A nonprofit research and development organization in Cambridge, MA, is seeking a motivated UVM Digital Verification Engineer. The role involves tackling verification challenges within FPGAs and ASICs. Candidates should have 3-5 years of experience or relevant master's experience, focusing on skills such as integrated circuit design and problem-solving in a collaborative environment. The position offers a salary range of $75,000 to $150,000, plus benefits and opportunities for work-life balance.

Qualifications

• 3-5 years with a bachelor's degree or 0-2 years with a master's degree in related field.
• Familiarity with major industry simulators.
• Experience in constrained-random testing.

Responsibilities

• Design and simulate circuits at transistor-level.
• Contribute to complex chip architectures and designs.
• Develop verification approaches and plans.

Skills

Integrated circuit design

Problem-solving skills

Verbal communication

Organizational skills

Mathematical skills

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

System Verilog

UVM

Questasim

Linux

Job description

A nonprofit research and development organization in Cambridge, MA, is seeking a motivated UVM Digital Verification Engineer. The role involves tackling verification challenges within FPGAs and ASICs. Candidates should have 3-5 years of experience or relevant master's experience, focusing on skills such as integrated circuit design and problem-solving in a collaborative environment. The position offers a salary range of $75,000 to $150,000, plus benefits and opportunities for work-life balance.