Senior Digital Verification Engineer (FPGA/ASIC)

Draper; Cambridge (MA); On-site; USD 75,000 - 156,000; Full time

Job summary

Draper in Cambridge, MA seeks a motivated UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital/mixed-signal designs in embedded security, cryptography, and signal processing.

Responsibilities include designing transistor-level circuits, developing verification plans, and building UVM environments for industry-standard buses.

Qualifications

• Bachelor's degree in Engineering or related field; master's preferred.
• 3–5 years of experience with IC/ASIC hardware engineering or 0–2 years with master's degree.
• Experience with digital verification methodologies and UVM/UVM-FF is desirable.
• Ability to design, verify, and optimize transistor-level circuits and architectures.
• Strong communication and collaboration in multi-disciplinary teams.

Responsibilities

• Design and simulate circuits at transistor level to meet specs.
• Develop verification plans and UVM environments for FPGA/ASIC.
• Create and optimize test benches and cover groups.
• Collaborate with RTL designers to resolve issues in simulation.
• Guide verification efforts and mentor junior engineers.

Skills

UVM

SystemVerilog

Verification

RTL Design

Python

C

Debugging

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

QuestaSim

Xcelium

VCS

Python

Perl

Job description

Draper in Cambridge, MA seeks a motivated UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital/mixed-signal designs in embedded security, cryptography, and signal processing.

Responsibilities include designing transistor-level circuits, developing verification plans, and building UVM environments for industry-standard buses.