Senior UVM Verification Engineer — FPGA/ASIC, Security Focus

Draper; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Benefits offered by this job

Work-life balance programs

Flexible work options

Employee clubs

Job summary

Draper in Cambridge, MA seeks a Senior UVM Digital Verification Engineer to tackle novel verification challenges for FPGAs and ASICs. You will apply modern verification strategies to embedded security, cryptography, and signal processing in a collaborative, multi-disciplinary setting.

You will develop verification plans, create UVM agents, and work with RTL designers to resolve issues while mentoring junior engineers. A strong background in SystemVerilog and Linux is required.

Qualifications

• Bachelor's degree in an engineering field; Master’s preferred.
• Experience with UVM-based verification and RTL design.
• Strong knowledge of SystemVerilog and verification methodologies.

Responsibilities

• Develop verification approaches and verification plans.
• Create and maintain UVM agents for proprietary buses.
• Instantiate VIPs for industry-standard buses and debug issues.
• Mentor junior engineers and perform code reviews.
• Collaborate across multidisciplinary teams including RTL designers.

Skills

UVM

SystemVerilog

Formal Analysis

Python

Linux

DDR3/DDR4

AXI/AMBA

Education

Bachelor's degree in Electrical Engineering

Master's degree

Tools

QuestaSim

Xcelium

VCS

Job description

Draper in Cambridge, MA seeks a Senior UVM Digital Verification Engineer to tackle novel verification challenges for FPGAs and ASICs. You will apply modern verification strategies to embedded security, cryptography, and signal processing in a collaborative, multi-disciplinary setting.

You will develop verification plans, create UVM agents, and work with RTL designers to resolve issues while mentoring junior engineers. A strong background in SystemVerilog and Linux is required.