UVM Digital Verification Engineer — FPGA/ASIC

Draper; Cambridge (MA); On-site; USD 75,000 - 156,000; Full time

Benefits offered by this job

Work-life balance

Employee clubs

Discounts to local museums

Job summary

Draper, a Cambridge, MA-based nonprofit R&D organization, seeks a motivated UVM Digital Verification Engineer to tackle challenging verification for FPGAs and ASICs. You will develop verification strategies, build UVM-based testbenches, and collaborate with RTL teams to ensure robust, secure hardware designs.

You will work in a multidisciplinary environment, contributing to embedded security, cryptography, and signal processing projects.

Qualifications

• Requires a bachelor's degree in Engineering or related field.
• 3–5 years of IC/ASIC hardware verification experience (or 0–2 years with a master's).
• Proficiency in IC design principles and architecture.
• Strong communication and documentation skills.

Responsibilities

• Develop verification approaches and verification plans.
• Author and execute UVM-based testbenches and agents.
• Create VIPs for industry-standard buses and manage covergroups.
• Collaborate with RTL designers to resolve issues and drive coverage to closure.
• Mentor junior engineers and perform code reviews.

Skills

IC design

Hardware architecture

SystemVerilog

UVM

SVA

Formal analysis

Problem solving

Communication

Planning & scheduling

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

SystemVerilog

SVA

UVM

QuestaSim

Xcelium

VCS

Job description

Draper, a Cambridge, MA-based nonprofit R&D organization, seeks a motivated UVM Digital Verification Engineer to tackle challenging verification for FPGAs and ASICs. You will develop verification strategies, build UVM-based testbenches, and collaborate with RTL teams to ensure robust, secure hardware designs.

You will work in a multidisciplinary environment, contributing to embedded security, cryptography, and signal processing projects.