Senior Design Verification Engineer

Mirafra Technologies; United States; Remote; USD 120,000 - 160,000; Full time

Job summary

Mirafra Technologies seeks a verification engineer to develop and verify complex systems using SystemVerilog and UVM. You will contribute to the verification of digital designs by building testbenches, debugging issues, and documenting results.

The role requires a solid understanding of hardware design, strong debugging skills, and experience with simulation tools. Bachelor's is required; Master’s is a plus, with a collaborative team environment in a technology-forward company.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Master's degree is a plus.
• Proficiency in SystemVerilog and UVM required.
• Strong understanding of digital design concepts.
• Experience with simulation tools and methodologies.

Responsibilities

• Develop and implement testbenches using SystemVerilog and UVM.
• Collaborate with design engineers to understand specifications and requirements.
• Perform functional verification of digital designs.
• Debug and troubleshoot issues in the verification environment.
• Document verification plans and results.

Skills

SystemVerilog

UVM

Digital design concepts

Simulation tools

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree is a plus

Job description

We are a leading technology company dedicated to innovation and excellence in the field of software development. Our mission is to create cutting-edge solutions that empower businesses and enhance user experiences. We foster a collaborative culture that values diversity, creativity, and continuous learning.

About the Role

The successful candidate will play a crucial role in the development and verification of complex systems using System Verilog and UVM methodologies. This position requires a strong understanding of hardware design and verification processes.

Responsibilities

• Develop and implement testbenches using System Verilog and UVM.
• Collaborate with design engineers to understand specifications and requirements.
• Perform functional verification of digital designs.
• Debug and troubleshoot issues in the verification environment.
• Document verification plans and results.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Master's degree is a plus.

Required Skills

• Proficiency in System Verilog and UVM.
• Strong understanding of digital design concepts.
• Experience with simulation tools and methodologies.

Preferred Skills

• Familiarity with other verification methodologies.
• Experience in a team-oriented environment.
• Knowledge of scripting languages such as Python or Perl.

Equal Opportunity Statement

We are an equal opportunity employer and are committed to fostering an inclusive environment for all employees. We celebrate diversity and are dedicated to creating a workplace where everyone feels valued and respected.