Senior FPGA Verification Engineer - SystemVerilog & UVM

Teradyne; San Jose (CA); On-site; USD 135,400 - 216,600; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Retirement savings plans

Tuition assistance

Job summary

Teradyne is seeking a Digital Functional Verification Engineer to drive planning, strategy, and execution of challenging FPGA verification projects. You will work under the supervision of a Verification Lead, interfacing with Hardware, Software, and Applications teams to ensure robust designs.

The role requires a strong background in SystemVerilog/UVM, verification planning, and Xcelium/Simvision tooling, with experience in standard protocols and IP integration.

Qualifications

• Master’s or equivalent with 6+ years experience or Bachelor’s with 8+ years.
• Experience with Verification Test Plan (Cadence ePlanner).
• Experience with EDA Tools (Cadence Xcelium, Simvision).
• SystemVerilog/UVM based verification and coverage.
• UVM testbench components development and integration.
• UVM tests sequences development and testing.
• Verification IP integration expertise.
• SystemVerilog/UVM reference models development and integration.
• Experience with AXI, PCIe, DDR3/4/5 protocols.
• Experience with revision control (ClearCase, Git, SVN).
• Detail-oriented with issue closure.

Responsibilities

• Plan, strategy and execution of FPGA verification projects.
• Interact with Hardware, Software and Applications groups under supervision.

Skills

SystemVerilog

UVM (tests/sequences)

Assertions & Coverage

Verification IP integration

Testbench development

AXI/PCIe/DDR protocols

Revision control (Git/SVN/CC)

Education

Master’s Degree in EE/CE/CS

Bachelor’s Degree in EE/CE/CS

Tools

Cadence Xcelium

Cadence Simvision

Job description

Teradyne is seeking a Digital Functional Verification Engineer to drive planning, strategy, and execution of challenging FPGA verification projects. You will work under the supervision of a Verification Lead, interfacing with Hardware, Software, and Applications teams to ensure robust designs.

The role requires a strong background in SystemVerilog/UVM, verification planning, and Xcelium/Simvision tooling, with experience in standard protocols and IP integration.