FPGA Verification Engineer: SystemVerilog/UVM Expert

Teradyne; North Reading (MA); On-site; USD 99,000 - 158,000; Full time

Job summary

Teradyne in North Reading, MA is seeking a Digital Logic Verification Engineer for the Logic Design Engineering team. The role focuses on FPGA verification, collaborating with cross-functional teams to deliver high-quality designs.

You will write and review verification plans, develop testbenches, create reference models, and work with SystemVerilog and UVM while gaining experience with Cadence Xcelium. The position offers a base salary range and eligible discretionary bonus.

Qualifications

• 3+ years of professional experience in digital logic verification or related roles.
• Experience with Cadence Xcelium or other industry-standard simulators.
• Strong experience with SystemVerilog and Universal Verification Methodology (UVM).
• Working knowledge of IP protocols (e.g., SPI, AXI, DDR).
• Experience with RTL design using Verilog HDL.
• Familiarity with SystemVerilog assertion-based verification methodologies.
• Experience working within CI/CD development flows.

Responsibilities

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write SystemVerilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader

Skills

SystemVerilog

UVM

Verilog HDL

CI/CD

RTL design

Debugging

Tools

Cadence Xcelium

UVM environments

Job description

Teradyne in North Reading, MA is seeking a Digital Logic Verification Engineer for the Logic Design Engineering team. The role focuses on FPGA verification, collaborating with cross-functional teams to deliver high-quality designs.

You will write and review verification plans, develop testbenches, create reference models, and work with SystemVerilog and UVM while gaining experience with Cadence Xcelium. The position offers a base salary range and eligible discretionary bonus.