Verification Engineer

Realtime Recruitment; Dallas (TX); On-site; USD 60,000 - 100,000; Full time

Job summary

A forward-thinking company is on the lookout for a motivated Junior Verification Engineer to join their dynamic digital hardware verification team. In this entry-level role, you'll work closely with experienced engineers to develop UVM-based verification plans and maintain SystemVerilog testbenches. You'll be involved in functional and regression testing of digital hardware components, ensuring designs meet industry standards. This is a fantastic opportunity to enhance your skills in a collaborative environment while contributing to innovative projects in the telecommunications and staffing sectors. If you have a passion for embedded systems and hardware design, this is the perfect role for you.

Qualifications

• Foundational experience in UVM-based verification is essential.
• Hands-on experience with C/C++ in verification or embedded systems.

Responsibilities

• Collaborate on UVM-based verification plans for FPGA and ASIC designs.
• Develop SystemVerilog testbenches and perform functional testing.

Skills

UVM-based verification

SystemVerilog

C/C++

Python

Perl

Analytical skills

Problem-solving skills

Communication skills

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Bachelor’s degree in a related field

Tools

ModelSim

QuestaSim

Job description

Direct message the job poster from Realtime Recruitment

IT Recruitment Consultant USA

Job Overview:

We are seeking a motivated and detail-oriented Junior Verification Engineer to join our digital hardware verification team. The ideal candidate will have foundational experience in UVM-based verification and a passion for embedded systems and hardware design. This role offers the opportunity to work alongside senior engineers in developing robust verification environments and test strategies.

Key Responsibilities:

• Collaborate with senior engineers to define and implement UVM-based verification plans for FPGA and ASIC designs.
• Develop and maintain SystemVerilog testbenches, test cases, and automation scripts.
• Perform functional and regression testing of digital hardware components.
• Analyze simulation results, identify bugs, and assist in debugging and issue resolution.
• Document verification procedures, test results, and track defects using standard tools.
• Ensure designs meet industry standards and project-specific requirements.
• Stay current with evolving verification methodologies and tools to continually improve processes.

Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of SystemVerilog and the Universal Verification Methodology (UVM).
• Hands-on experience with C/C++ in the context of verification or embedded systems.
• Familiarity with scripting languages such as Python or Perl for automation tasks.
• Exposure to simulation tools like ModelSim, QuestaSim, or similar.

Desired Skills:

• Strong analytical and problem-solving skills with a keen eye for detail.
• Effective communication and teamwork skills in a collaborative engineering environment.
• Enthusiastic learner with the ability to adapt to new technologies and methodologies.

Seniority level

• Entry level

Employment type

• Full-time

Job function

• Information Technology

Industries

• Staffing and Recruiting
• Telecommunications