FPGA & ASIC Verification Engineer - SystemVerilog/UVM

Teradyne; Reading (MA); On-site; USD 99,000 - 158,000; Full time

Benefits offered by this job

Health benefits

Tuition assistance

Paid vacation

Retirement plan

Life insurance

Job summary

Teradyne is seeking a Digital Logic Verification Engineer at our North Reading, MA center to focus on FPGA verification and related RTL work. You will collaborate with cross-functional teams to deliver robust designs, developing testbenches and UVM environments, and ensuring high coverage through systematic debugging and reviews.

The role requires 3+ years in digital logic verification, proficiency with SystemVerilog/UVM, and hands-on experience with Cadence Xcelium.

Qualifications

• 3+ years of professional experience in digital logic verification or related roles.
• Experience with Cadence Xcelium or other industry-standard simulators.
• Strong experience with SystemVerilog and Universal Verification Methodology (UVM).
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR).
• Experience with RTL design using Verilog HDL.
• Familiarity with SystemVerilog assertion-based verification methodologies.
• Experience working within CI/CD development flows.

Responsibilities

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader

Skills

SystemVerilog

UVM

RTL Verilog

CI/CD pipelines

Debugging

Testbenches

Tools

Cadence Xcelium

Job description

Teradyne is seeking a Digital Logic Verification Engineer at our North Reading, MA center to focus on FPGA verification and related RTL work. You will collaborate with cross-functional teams to deliver robust designs, developing testbenches and UVM environments, and ensuring high coverage through systematic debugging and reviews.

The role requires 3+ years in digital logic verification, proficiency with SystemVerilog/UVM, and hands-on experience with Cadence Xcelium.