FPGA Design Verification Engineer - UVM & SV Expert

Altera; United States; Remote; USD 9,400 - 16,000; Full time

Job summary

Altera is seeking a talented Design Verification Engineer to design, develop, validate, and debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

You will build robust UVM-based testbenches, write SystemVerilog assertions, create directed and randomized tests, and collaborate with architects and design engineers to validate IP specifications. Strong scripting skills in Python or Perl are required.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in ASIC or FPGA design verification.
• Expertise in Verilog or VHDL and SystemVerilog HVL.
• Strong hands-on experience with UVM-based testbenches and verification components.
• Proficiency in CDV and ABV methodologies.
• Familiarity with AMBA (AXI, ACE, CHI, APB), PCIe or Ethernet is a plus.
• Experience with simulation and debugging tools.
• Scripting skills in Python, Perl, or Tcl for automation and data analysis.
• Excellent analytical, problem-solving, and debugging skills.
• Strong communication and collaboration abilities.

Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define verification strategies and test plans.
• Develop robust, reusable verification environments using SystemVerilog and UVM.
• Create directed and random test cases to exercise design functionality and uncover bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions and formal verification to enhance bug detection.
• Run simulations, debug test failures, analyze root causes, and implement corrective measures with designers.
• Define and track functional and code coverage to ensure verification completeness.
• Develop automation scripts to improve verification efficiency and flows (Python/Perl/Tcl).
• Participate in technical reviews of specifications, designs, and test plans.

Skills

SystemVerilog

Verilog

VHDL

UVM

SystemVerilog Assertions

CDV

ABV

Python scripting

Perl scripting

Tcl scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

Altera is seeking a talented Design Verification Engineer to design, develop, validate, and debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

You will build robust UVM-based testbenches, write SystemVerilog assertions, create directed and randomized tests, and collaborate with architects and design engineers to validate IP specifications. Strong scripting skills in Python or Perl are required.