TPU ML Hardware Architect for AI Compute

Socket.dev; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is shaping AI/ML hardware acceleration in Sunnyvale, CA. You’ll drive TPU innovations, collaborating with Hardware, Software, Compiler, ML model teams to optimize performance and power for next-gen TPUs in real-world workloads.

You will prototype features, model performance, and ensure integration across training and inference pipelines while advancing ML accelerator efficiency.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 8+ years of experience in computer architecture, chip architecture, IP architecture, co-design, performance analysis, or hardware design.
• Experience developing software systems in C++ or Python.

Responsibilities

• Create differentiated architectural innovations for Google’s TPU roadmap.
• Evaluate power, performance, and cost of prospective architectures and subsystems.
• Collaborate with Hardware Design, Software, Compiler, ML Model and Research teams for hardware/software co-design.
• Work on ML workload characterization and benchmarking.
• Develop architecture for differentiating features on next generation TPUs.

Skills

C++

Python

ML framework experience

Hardware/software co-design

System performance analysis

DL accelerator knowledge

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science or related field

Master's or PhD in Electrical/CE/CS with emphasis on Computer Architecture

8+ years of experience in computer architecture or related field

Job description

Google is shaping AI/ML hardware acceleration in Sunnyvale, CA. You’ll drive TPU innovations, collaborating with Hardware, Software, Compiler, ML model teams to optimize performance and power for next-gen TPUs in real-world workloads.

You will prototype features, model performance, and ensure integration across training and inference pipelines while advancing ML accelerator efficiency.