TPU SoC Integration Lead

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is hiring an ASIC SoC Integration Engineer to shape the future of AI/ML hardware acceleration. You will drive TPU technology powering Google's demanding AI/ML applications and develop custom silicon solutions with a focus on TPU architecture and its integration in AI/ML-driven systems.

In this role you will manage RTL and SoC IP integration, collaborate with Verification/Emulation teams, and own RTL hierarchy up to the package level while addressing signaling and physical design concerns

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in ASIC design or RTL design.
• Experience with SoC design and integration.
• Experience with multi-chiplet SoC integration.
• Experience with SoC Design for Testing (DFT) planning.
• Experience scripting in Python or Perl or Tcl.

Responsibilities

• Lead advanced SoC integration projects from concept to final delivery, managing milestones, deliverables, and cross-functional schedules.
• Partner with ASIC teams on complex interposer and package design, and resolve multi-die physical design challenges leveraging 3DIO and domain partitioning expertise.
• Utilize software-based construction to seamlessly integrate SoC IPs and maintain complete ownership of the upper-level RTL hierarchy up to the package level.
• Collaborate closely with Verification and Emulation teams to resolve complex connectivity issues and optimize system compilation.
• Participate in critical layout design decisions and SoC-level sign-off activities to ensure robust, high-performance silicon delivery.

Skills

ASIC design

RTL design

SoC integration

multi-chiplet SoC

DFT planning

Python/Perl/Tcl scripting

Education

Bachelor's degree

Master's degree

PhD

Job description

Google is hiring an ASIC SoC Integration Engineer to shape the future of AI/ML hardware acceleration. You will drive TPU technology powering Google's demanding AI/ML applications and develop custom silicon solutions with a focus on TPU architecture and its integration in AI/ML-driven systems.

In this role you will manage RTL and SoC IP integration, collaborate with Verification/Emulation teams, and own RTL hierarchy up to the package level while addressing signaling and physical design concerns