TPU SoC Integration Architect

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

The opportunity at Google Inc. centers on shaping the future of AI/ML hardware acceleration via TPU technology.

You will drive multi-chiplet SoC integration, architect RTL, and coordinate with Verification and Emulation teams to ensure robust silicon delivery for Google’s TPU family. As an ASIC SoC Integration Engineer, you’ll own RTL up to the package level, collaborate on interposer packaging, and plan multi-die DFT connectivity, while guiding cross-functional teams toward project milestones

Qualifications

• 8 years of experience in ASIC design or RTL design.
• Experience with SoC design and integration.
• Experience with multi-chiplet SoC integration.
• Experience with SoC Design for Testing (DFT) planning.
• Experience scripting in Python or Perl or Tcl.

Responsibilities

• Lead advanced SoC integration projects from concept to final delivery.
• Collaborate with ASIC teams on interposer and packaging design to address multi-die challenges.
• Own RTL hierarchy up to the package level and coordinate with Verification teams.
• Manage RTL deliverables and plan integration activities to meet schedules.
• Verify complex digital designs with focus on TPU architecture in AI/ML systems.

Skills

ASIC/RTL design

SoC integration

DFT planning

Python/Perl/Tcl scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

The opportunity at Google Inc. centers on shaping the future of AI/ML hardware acceleration via TPU technology.

You will drive multi-chiplet SoC integration, architect RTL, and coordinate with Verification and Emulation teams to ensure robust silicon delivery for Google’s TPU family. As an ASIC SoC Integration Engineer, you’ll own RTL up to the package level, collaborate on interposer packaging, and plan multi-die DFT connectivity, while guiding cross-functional teams toward project milestones