TPU RTL Design Engineer for AI/SoC Accelerators

Google LLC; Sunnyvale (CA); Presencial; USD 163.000 - 236.000; Jornada completa

Descripción de la vacante

Google Sunnyvale, CA, USA is seeking an experienced RTL/ASIC design engineer to shape the future of AI/ML hardware acceleration. You will drive cutting-edge TPU technology and develop custom silicon solutions powering Google's TPU, verifying complex digital designs with emphasis on TPU architecture integration in AI/ML systems.

You will work on SoC-level RTL design for data center accelerators, designing RTL IP with focus on management and control subsystems, and co-design with software and

Formación

• Bachelor's degree or equivalent practical experience.
• Experience with scripting languages.
• Master's or PhD with emphasis on computer architecture.
• 8 years of ASIC design experience.
• Experience interacting with software, system hardware, and cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals (I2C, SPI, UART).
• Understanding of digital design fundamentals (synchronous/asynchronous logic, state machines, bus protocols).

Responsabilidades

• Design RTL IP focused on the management and control subsystem.
• Develop SystemVerilog RTL to implement logic for ASIC products per guidelines.
• Coordinate with architecture, DV, and physical design teams to ensure timing and integration.
• Lead multidisciplinary efforts across software and system hardware counterparts.
• Contribute to the development infrastructure and methodologies for SoCs.

Conocimientos

ASIC design

RTL design

Digital logic

Educación

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS (computer architecture)

Herramientas

SystemVerilog

Descripción del empleo

Google Sunnyvale, CA, USA is seeking an experienced RTL/ASIC design engineer to shape the future of AI/ML hardware acceleration. You will drive cutting-edge TPU technology and develop custom silicon solutions powering Google's TPU, verifying complex digital designs with emphasis on TPU architecture integration in AI/ML systems.

You will work on SoC-level RTL design for data center accelerators, designing RTL IP with focus on management and control subsystems, and co-design with software and