AI/ML Compute RTL Design Manager

Google LLC; Sunnyvale (CA); On-site; USD 256,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target (20%)

Benefits package

Job summary

Google LLC in Sunnyvale, CA is seeking a Silicon Compute RTL Design Manager to shape the future of TPU hardware and AI/ML acceleration. You will lead RTL design engineers, drive architectural feasibility, and collaborate with Architecture, Verification, and Software teams to deliver high-performance TPU cores.

This role requires extensive experience in chip design, SystemVerilog, and people management, with a focus on performance, power, and scalable silicon solutions powering Google's AI

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• 10 years of experience with chip design, ASIC digital design, and SystemVerilog.
• 8 years of experience in computer architecture and RTL.
• 3 years in people management and developing employees.

Responsibilities

• Lead, mentor, and manage RTL Design Engineers for IP development of Compute Cores.
• Provide technical leadership and model best design practices (micro-architecture, reviews, methodology).
• Act as primary design contact; participate with Architecture and System Design on feasibility, power, and performance.
• Collaborate with Verification, Design for Test, Physical Design, and Software across projects.
• Drive improvements in design methodologies, processes, and quality control.

Skills

Chip design

ASIC digital design

SystemVerilog

Computer architecture

RTL design

People management

Technical leadership

Design reviews

Cross-functional collaboration

Clocking & power management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD in Electrical/Computer Engineering or Computer Science

Job description

Google LLC in Sunnyvale, CA is seeking a Silicon Compute RTL Design Manager to shape the future of TPU hardware and AI/ML acceleration. You will lead RTL design engineers, drive architectural feasibility, and collaborate with Architecture, Verification, and Software teams to deliver high-performance TPU cores.

This role requires extensive experience in chip design, SystemVerilog, and people management, with a focus on performance, power, and scalable silicon solutions powering Google's AI