TPU RTL Design Engineer for AI Acceleration

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC is seeking an RTL Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and its integration within AI/ML-driven systems. You will contribute to cutting-edge silicon solutions powering Google's AI capabilities for data centers.

You will join a team responsible for SoC-level RTL design for data center accelerators, designing RTL IP with emphasis on chassis infrastructure, fabric bridges, and sensor telemetry networks, collaborating across

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Responsibilities

• Work independently to create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

ASIC RTL design

SystemVerilog

Python/Tcl/Perl scripting

Clocking/Reset/Timing

Education

Bachelor's in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Job description

Google LLC is seeking an RTL Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and its integration within AI/ML-driven systems. You will contribute to cutting-edge silicon solutions powering Google's AI capabilities for data centers.

You will join a team responsible for SoC-level RTL design for data center accelerators, designing RTL IP with emphasis on chassis infrastructure, fabric bridges, and sensor telemetry networks, collaborating across