TPU ASIC Design Engineer – Microarchitecture & Power

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Bonus potential

Job summary

Google LLC in Sunnyvale, California, seeks a seasoned RTL design engineer to shape the TPU microarchitecture and lead digital design within AI hardware accelerators. You will collaborate across Verification, Physical Design, and firmware to meet performance, power, and area goals while enabling scalable, production-grade silicon.

The role emphasizes on-chip-network design, integration with AI/ML systems, and driving automation across design tools and flows.

Qualifications

• Bachelor's degree in ECE/CS or equivalent.
• 8 years of RTL design experience.
• Experience with digital design and microarchitecture design.
• Experience in optimizing for performance, power, and area.
• Cross-functional experience with DV and PD teams.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL.
• Collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.
• Support post-silicon validation and hardware debugging efforts to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Skills

RTL design

Digital design

Microarchitecture

Perf/Power/Area optimization

DV/PD collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

Job description

Google LLC in Sunnyvale, California, seeks a seasoned RTL design engineer to shape the TPU microarchitecture and lead digital design within AI hardware accelerators. You will collaborate across Verification, Physical Design, and firmware to meet performance, power, and area goals while enabling scalable, production-grade silicon.

The role emphasizes on-chip-network design, integration with AI/ML systems, and driving automation across design tools and flows.