ASIC Design Engineer, Cloud TPU

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Bonus potential

Job summary

Google LLC in Sunnyvale, California, seeks a seasoned RTL design engineer to shape the TPU microarchitecture and lead digital design within AI hardware accelerators. You will collaborate across Verification, Physical Design, and firmware to meet performance, power, and area goals while enabling scalable, production-grade silicon.

The role emphasizes on-chip-network design, integration with AI/ML systems, and driving automation across design tools and flows.

Qualifications

• Bachelor's degree in ECE/CS or equivalent.
• 8 years of RTL design experience.
• Experience with digital design and microarchitecture design.
• Experience in optimizing for performance, power, and area.
• Cross-functional experience with DV and PD teams.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL.
• Collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.
• Support post-silicon validation and hardware debugging efforts to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Skills

RTL design

Digital design

Microarchitecture

Perf/Power/Area optimization

DV/PD collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

Job description

Minimum qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

8 years of experience in RTL design.

Experience with digital design and microarchitecture design.

Experience in optimizing for performance, power, and area.

Cross-functional experience with Design Verification (DV) and Physical Design (PD) teams.

Preferred qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

10 years of RTL design experience.

4 years of experience in power optimization and experience with power analysis tools like PowerArtist and PTPX.

Experience with Linting, CDC, RDC, LEC and experience with Scripting languages (i.e. Python or Perl).

Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.

Experience in design automation, architecting RTL solutions and ASIC Synthesis flows.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. Your role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.


• Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.


• Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.


• Support post-silicon validation and hardware debugging efforts to ensure successful deployment.


• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Pay & Benefits

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

Company culture & inclusion

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .