TPU Architecture Modeling Engineer

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity grants

Benefits

Job summary

Google is seeking a Hardware Architecture Modeling Engineer to shape the future of AI/ML hardware acceleration and drive TPU technology. You will join a team refining custom silicon solutions powering Google's demanding AI workloads and collaborate with hardware, software, and ML teams.

In this role you will model, analyze, and define next-generation TPUs, working with architects to enable quantitative analysis, performance, and power optimization across cloud-scale systems.

Qualifications

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• Experience in any one domain of computer engineering or silicon engineering through internships, academic research, or publications (e.g., co-design, digital design, architecture).
• Experience programming in C++ or Python.

Responsibilities

• Develop architectural and micro architectural models to enable quantitative analysis.
• Conduct performance and power analyses and evaluate proposals.
• Contribute to ML workload characterization, benchmarking, and hardware-software co-design.
• Collaborate with hardware design, software, compiler, ML model and research teams for codesign.
• Propose capabilities and next-generation TPUs and chip roadmap; contribute to TPUs specs.

Skills

C++

Python

Co-design

Digital design

Architecture

AI/ML hardware acceleration

Education

PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

Job description

Google is seeking a Hardware Architecture Modeling Engineer to shape the future of AI/ML hardware acceleration and drive TPU technology. You will join a team refining custom silicon solutions powering Google's demanding AI workloads and collaborate with hardware, software, and ML teams.

In this role you will model, analyze, and define next-generation TPUs, working with architects to enable quantitative analysis, performance, and power optimization across cloud-scale systems.