TPU ASIC Verification Engineer (AI Hardware)

Google LLC

Sunnyvale (CA)

On-site

USD 138,000 - 197,000

Full time

4 days ago
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Job summary

Google is seeking an ASIC Design Verification Engineer to shape the TPU hardware verification effort in Sunnyvale, CA. You will verify complex digital designs and drive TPU architecture integration within AI/ML systems, contributing to Google's cutting-edge AI hardware.

In this role you will perform direct verification on active projects and develop verification strategies using SystemVerilog/Verilog, UVM, and constrained-random techniques to ensure robust tape-out readiness.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, CS or related field.
  • 4 years of experience with design verification.
  • Experience with SystemVerilog/Verilog.

Responsibilities

  • Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Identify and write all types of coverage measures for stimulus and corner cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
  • Create a constrained-random verification environment using SystemVerilog and UVM.

Skills

SystemVerilog/Verilog
Design verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog/Verilog

Job description

Google is seeking an ASIC Design Verification Engineer to shape the TPU hardware verification effort in Sunnyvale, CA. You will verify complex digital designs and drive TPU architecture integration within AI/ML systems, contributing to Google's cutting-edge AI hardware.

In this role you will perform direct verification on active projects and develop verification strategies using SystemVerilog/Verilog, UVM, and constrained-random techniques to ensure robust tape-out readiness.

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