TPU Compute ASIC Verification Lead

Google LLC; Sunnyvale (CA); On-site; USD 256,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target 20%

Benefits

Job summary

Google is seeking an experienced ASIC Design Verification Manager for TPU Compute in Sunnyvale, CA. You will lead a team responsible for the functional verification of key TPU components, shaping verification infrastructure across subchip to full-chip levels.

The role emphasizes collaboration with front-end design, architecture, and performance teams to ensure architectural compliance, functional correctness, and high-performance outcomes in AI/ML accelerators.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 10 years of verification, SystemVerilog, and UVM.
• 3 years of people management.

Responsibilities

• Lead the functional verification team for TPU Compute, setting priorities and coaching team members.
• Define and drive comprehensive verification strategies for complex compute subsystems.
• Architect scalable, reusable verification environments and flows.
• Provide technical leadership, conduct code reviews, and establish verification quality standards.
• Collaborate with architects and design leads to improve verification throughput and overall quality.

Skills

Verification

SystemVerilog

UVM

People management

Cross-functional leadership

Test planning

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Industry verification tools

Job description

Google is seeking an experienced ASIC Design Verification Manager for TPU Compute in Sunnyvale, CA. You will lead a team responsible for the functional verification of key TPU components, shaping verification infrastructure across subchip to full-chip levels.

The role emphasizes collaboration with front-end design, architecture, and performance teams to ensure architectural compliance, functional correctness, and high-performance outcomes in AI/ML accelerators.