Senior ASIC Verification Engineer - Cloud AI/TPU RTL/UVM

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google LLC in Sunnyvale, CA seeks an ASIC Design Verification Engineer to help shape the future of AI/ML hardware acceleration. You will verify complex digital designs, focus on TPU architecture, and contribute to data-center accelerators with SystemVerilog/UVM.

The role involves in-person interviews and collaboration with design engineers to drive tape-out readiness and a robust verification flow for Google's TPU technology.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with design verification.
• Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.

Responsibilities

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

SystemVerilog/UVM

RTL verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture

Tools

SystemVerilog

UVM

Job description

Google LLC in Sunnyvale, CA seeks an ASIC Design Verification Engineer to help shape the future of AI/ML hardware acceleration. You will verify complex digital designs, focus on TPU architecture, and contribute to data-center accelerators with SystemVerilog/UVM.

The role involves in-person interviews and collaboration with design engineers to drive tape-out readiness and a robust verification flow for Google's TPU technology.