Lead, Physical Design for AI ASIC TPU

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC Sunnyvale, CA is seeking a Physical Design Technical Lead for ASIC TPU to drive end-to-end physical design for next-generation AI silicon.

The role requires a Bachelor's degree and 10 years of physical design experience with RTL2GDSII, floorplanning, place-and-route, and timing closure. Proficiency in Python, Tcl, or Perl is expected. This is an on-site role with potential for collaboration across RTL/DFT/methodology/packaging teams.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
• Experience in Python, Tcl, or Perl scripting.

Responsibilities

• Lead physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Skills

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with emphasis on computer architecture

Tools

Cadence Innovus

Synopsys DP

Mentor Calibre

StarRC

Job description

Google LLC Sunnyvale, CA is seeking a Physical Design Technical Lead for ASIC TPU to drive end-to-end physical design for next-generation AI silicon.

The role requires a Bachelor's degree and 10 years of physical design experience with RTL2GDSII, floorplanning, place-and-route, and timing closure. Proficiency in Python, Tcl, or Perl is expected. This is an on-site role with potential for collaboration across RTL/DFT/methodology/packaging teams.