ASIC Verification Engineer - AI/ML TPU Architect

Google LLC; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking an ASIC Design Verification Engineer for the TPU team to shape AI/ML hardware acceleration. You will verify complex digital designs focusing on TPU architecture and its integration within AI/ML systems.

You will collaborate with design engineers, create constrained-random environments with SystemVerilog and UVM, and drive verification coverage to support tape-out while contributing across the design and verification life cycle.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.

Responsibilities

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Identify and write all types of coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Create a constrained-random verification environment using SystemVerilog and UVM.

Skills

SystemVerilog/Verilog

Design verification

Education

Bachelor's degree in Electrical/Computer Engineering or CS

equivalent practical experience

Tools

Simulators

Revision control systems

Regression systems

Job description

Google LLC in Sunnyvale, CA is seeking an ASIC Design Verification Engineer for the TPU team to shape AI/ML hardware acceleration. You will verify complex digital designs focusing on TPU architecture and its integration within AI/ML systems.

You will collaborate with design engineers, create constrained-random environments with SystemVerilog and UVM, and drive verification coverage to support tape-out while contributing across the design and verification life cycle.