Timing Design Engineer (Part‑Time, $28/hr)

Apple; Sacramento (CA); Remote; USD 31,822 - 45,323; Part time

Benefits offered by this job

Health, dental, and vision coverage

Retirement savings plan

Employee Stock Purchase Program

Job summary

Apple in Sacramento, CA is seeking a Timing Design Engineer on a part-time basis. The role focuses on block-level static timing analysis, clock networks, and timing closure for high-performance SOCs. Strong Verilog and STA experience are required.

You will collaborate with RTL/PD teams, generate ECOs, and help refine CAD methodologies while benefiting from comprehensive health, retirement, and stock options. Apple emphasizes growth support and educational reimbursements.

Qualifications

• Knowledge of high-performance PHY and SOC timing strategies.
• Understanding of industry guidelines and best practices in timing analysis and closure.
• Experience creating and executing STA (Static Timing Analysis) tasks.
• Strong grasp of the entire timing flow, from RTL to GDSII.
• Proficiency with SOC engineering concepts and HDL languages such as Verilog.
• Familiarity with timing tools and device libraries in a production environment.
• Experience scripting in languages such as Perl or Tcl for automation.

Responsibilities

• Create block-level static timing assertions
• Collaborate with RTL and PD groups to meet timing closure on basic blocks
• Develop and approve low-power clock network rules for high-performance execution
• Perform timing enhancements and approve plans for usability
• Generate and execute ECOs to correct timing issues
• Run chip and block-level timing checks and provide correction rules to designers
• Assist in defining and refining CAD and timing methodologies for process improvement
• Support stream optimization for chip coordination activities

Skills

PHY/SOC timing strategies

Timing guidelines & best practices

STA tasks

Timing flow RTL to GDSII

Verilog HDL

Timing tools & libraries

Perl/Tcl scripting

Education

Bachelor's degree

Job description

Apple in Sacramento, CA is seeking a Timing Design Engineer on a part-time basis. The role focuses on block-level static timing analysis, clock networks, and timing closure for high-performance SOCs. Strong Verilog and STA experience are required.

You will collaborate with RTL/PD teams, generate ECOs, and help refine CAD methodologies while benefiting from comprehensive health, retirement, and stock options. Apple emphasizes growth support and educational reimbursements.